UHS (SD-Card) clock frequency

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UHS (SD-Card) clock frequency

8,532 Views
oferfederovsky
Contributor III

Hi,

We have a custom board and we are trying to debug UHS.

Our board support switching to 1.8v, and it seems that we do work in UHS, but the SD clock frequency is ~50MHz.

From dmesg:

[    3.924535] sdhci: Secure Digital Host Controller Interface driver

[    3.930721] sdhci: Copyright(c) Pierre Ossman

[    3.935235] mmc0: no vmmc regulator found

[    3.939500] mmc0: SDHCI controller on platform [sdhci-esdhc-imx.0] using DMA

[    4.083747] regulator_init_complete: vmmc: incomplete constraints, leaving on

[    4.134227] sdhci_start_signal_voltage_switch

[    4.177389] mmc0: new ultra high speed SDHC card at address aaaa

[    4.184295] mmcblk0: mmc0:aaaa SU08G 7.40 GiB

[    4.190366]  mmcblk0: p1 p2

From our board-file:

static const struct esdhc_platform_data mx6_arm2_sd1_data __initconst = {

  .cd_gpio = SEEMORE_SD1_CD,

  .cd_type = ESDHC_CD_GPIO,

  .support_8bit   = 1,

  .keep_power_at_suspend  = 1,

  .cd_gpio_inverted = 1,

  .support_18v = 1,

};


Custom board with i.mx6q, Linux 3.0.35 4.1.0.


What should I do in order to switch to higher frequencies (104MHz)?


Thanks!

Ofer


Labels (2)
8 Replies

2,606 Views
igorpadykov
NXP Employee
NXP Employee

Hi Ofer

Linux 3.0.35 4.1.0 does not support UHS,

please try latest 3.10.17 where declared SD 3.0 support (UHS-I is part of it).


L3.10.17_1.0.0_IMX6QDLS_BUNDLE


Best regards

chip

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2,606 Views
oferfederovsky
Contributor III

Hi,

Thank you for your help,

Following your answer, I'm trying kernel 3.10.17_1.0.0, but now I see the following:

From dmesg:

sdhci: Secure Digital Host Controller Interface driver

sdhci: Copyright(c) Pierre Ossman

sdhci-pltfm: SDHCI platform and OF driver helper

sdhci-esdhc-imx 2190000.usdhc: could not get ultra high speed state, work on normal mode

mmc0: no vqmmc regulator found

mmc0: no vmmc regulator found

mmc0: SDHCI controller on 2190000.usdhc [2190000.usdhc] using ADMA

mmc0: host does not support reading read-only switch. assuming write-enable.

mmc0: new high speed SDHC card at address aaaa

mmcblk0: mmc0:aaaa SL08G 7.40 GiB

mmcblk0: p1 p2

From my device tree:

&usdhc1 {

  pinctrl-names = "default";

  pinctrl-0 = <&pinctrl_usdhc1_1>;

  status = "okay";

};

What am I missing?

Thanks!

Ofer

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2,606 Views
igorpadykov
NXP Employee
NXP Employee

Hi Ofer

SDR104 supported only on SD3,4 ports.

"For UHSI cards, clock speed fuses can be set to SDR50 or SDR104 on USDHC3 and

USDHC4 ports."

p.415 IMX6DQRM i.MX 6Dual/6Quad Applications Processor Reference Manual

Best regards

chip

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2,606 Views
oferfederovsky
Contributor III

Hi chipexpert,

Thanks again for your help.

It took some time and effort, but now I have a setup with uSDHC3.

Sadly, I still have this error: could not get ultra high speed state, work on normal mode.

(SD seems to work, but not in Ultra high speed).

I have this in my dts files:

&iomuxc {

     pinctrl-names = "default";

     pinctrl-0 = <&pinctrl_hog_1>;

          imx6q-ooo {

          pinctrl_hog_1: hoggrp-1 {

          fsl,pins = <

                MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059

          >;

          };

     };

};


&usdhc3 {

     pinctrl-names = "default";

     pinctrl-0 = <&pinctrl_usdhc3_1>;

     pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>;

     pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>;

     vqmmc-1-8-v = <1>;

     bus-width = <4>;

     status = "okay";

};

I monitored the vselect signal, and noticed that the vselect is in logical zero, until the kernel raises it into a logical "1".

When I monitored the data/cmd/clk signals, the voltage levels where at ~3v while I expected them to be 1.8v (while vselect is set).

I wonder if VSELECT PAD is configured correctly.

I'm attaching some HW info related to the VSELECT.

Also, shouldn't the VSELECT PAD be configured in imx6qdl.dtsi together with the rest of the uSDHC pads?

dmesg:

sdhci: Secure Digital Host Controller Interface driver

sdhci: Copyright(c) Pierre Ossman

sdhci-pltfm: SDHCI platform and OF driver helper

sdhci-esdhc-imx 2198000.usdhc: could not get ultra high speed state, work on normal mode

mmc0: no vqmmc regulator found

mmc0: no vmmc regulator found

mmc0: SDHCI controller on 2198000.usdhc [2198000.usdhc] using ADMA

mmc0: host does not support reading read-only switch. assuming write-enable.

mmc0: new high speed SDHC card at address aaaa

mmcblk0: mmc0:aaaa SU08G 7.40 GiB

mmcblk0: p1 p2

EXT4-fs (mmcblk0p1): warning: mounting unchecked fs, running e2fsck is recommended

EXT4-fs (mmcblk0p1): mounted filesystem without journal. Opts: (null)

EXT4-fs (mmcblk0p1): re-mounted. Opts: stripe=1024

You help is much appreciated! Thanks!

Ofer

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2,606 Views
宗標廖
Contributor V

Hello,

Ofer

Maybe you have resolved your problem,but I still give my remind.

You should set usdhc3 as below.

&usdhc3 {

     pinctrl-names = "default", "state_100mhz", "state_200mhz";

     pinctrl-0 = <&pinctrl_usdhc3_1>;

     pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>;

     pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>;

     vqmmc-1-8-v = <1>;

     bus-width = <4>;

     status = "okay";

};

Best Regards,

ZongbiaoLiao

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igorpadykov
NXP Employee
NXP Employee

Hi Ofer

you can refer to attached patches as example


Best regards

chip

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oferfederovsky
Contributor III

Hello chipexpert,

Now I'm very confused.

As I understand, these patches are for kernel 3.0.35.

On July-14 you suggested me to try Linux 3.10.17. I made some effort to bring up Linux 3.10.17 on my custom board.

So are you suggesting me to get back to 3.0.35?

What if I want to keep using kernel 3.10.17?

Regarding your answer from Aug-12:

The sentence speaks about clock speed fuses. Is it relevant if I'm only interested in Ultra high speed during normal operation (and not during power up)?

(Will Ultra high speed work on uSDHC1?)

Thanks again,
Ofer.

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2,606 Views
igorpadykov
NXP Employee
NXP Employee

Hi Ofer

unfortunately seems these are only codes what are

available. Next link may be useful

http://comments.gmane.org/gmane.linux.kernel.mmc/23339

Regarding "speed fuses":

do you think that if they would work on normal operation

this would not be supported at boot ?


Best regards

chip

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