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i.mx6 DDR3 64-bit ECC layout

Question asked by Andrew Kohlsmith on Jul 10, 2014
Latest reply on Jul 24, 2014 by Andrew Kohlsmith

I'm looking at using the i.MX6 in an application that requires ECC.

 

Specifically I am wondering if there are any layout recommendations for using 16-bit wide DDR3L in an ECC configuration (5 devices). Does the i.mx6 (dual or quad) support fly-by routing, or do I have to route such that the address and control lines are trace-length matched? Are there any issues with using "half" of the 16-bit DDR3L memory module for ECC, or do I have to use 9 8-bit wide devices?

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