AnsweredAssumed Answered

Freescale P1010 with Xilinx Virtex-6 communicating over PCIe.

Question asked by franka on Jul 9, 2014
Latest reply on Aug 21, 2014 by Nick Weyland

I am using a P1010 system with a Xilinx Virtex-6 FPGA.  The connection between the P1010 and the Virtex-6 is via the PCIe bus.  I am DMA'ing data from the Virtex-6 to the P1010 DDR memory.  The P1010 is root complex and the Virtex-6 is an endpoint.  There is nothing else on the PCIe bus.  The Virtex-6 appears to be throttled by the P1010.


I measure the speed of this PCIe link at 75MB/sec by timing large data transfers from the Virtex-6 to the P1010 on the P1010.


I would expect this PCIe link to transfer data faster.  I have a few general questions in regards to trying to improve this data transfer speed from 75MB/sec.

1) What is an achievable speed with PCIe and the P1010?  Am I at the limit for the P1010?

2) Do I need special techniques on the P1010 (e.g. L2 cache/stashing) to get higher data rates?  I am using a max payload size of 128 bytes.

3) Are there special kernel configurations that I may be missing that are selectable and can improve the speed?  I am using QorIQ-SDK-V1.2-20120614-yocto.

4) Are there special configuration settings in the P1010RDB.h config file (u-boot or kernel) that need to be changed?