TWR-MCF5441x + TWR-PROTO + Secondary Elevator ?= NAND flash Prolbems

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TWR-MCF5441x + TWR-PROTO + Secondary Elevator ?= NAND flash Prolbems

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stevejanisch
Contributor IV

I was wondering if anyone else has encountered NAND access problems when using a TWR-PROTO board in a TWR-MCF5441x system.

What I am experiencing is that if I put a TWR-PROTO board (even a blank prototype board) in the tower AND connect the secondary side elevator I can have problems with NAND.  This might include the bootloader not working (not properly loading and launching), MQX functions reporting bad NAND blocks, and/or checksum errors on stored images.

Interestingly, if I remove the secondary side elevator from the system, the NAND access is flawless.  In fact if I plug the TWR-MCF5441x and TWR-SER2 into the secondary and just bypass TWR-PROTO it also works.

It seems to be the combination of having the TWR-PROTO board in place AND connecting the secondary side elevator that cause the NAND flash problems.

But that sounds crazy, doesn't it?

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stevejanisch
Contributor IV

Maybe I solved this (maybe I didn't) but wanted to post findings just in case someone else runs into them.

Also changed Place from "Tower Geeks" to "MQX Software Solutions" since it appears more to do with the default MQX 4.0 PSP code for the MCF5441x.

In init_hw.c, MQX 4.0 changes the NAND clock from the default divide by 32 to a divide by 14.

If I return the NAND clock to the default, there are no NAND errors.

Why it worked without the secondary riser in place is unknown.  Perhaps having the third board and riser in place added enough capacitance or potential for interference.. I''m not really a hardware guy so can't really say.

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357 Views
stevejanisch
Contributor IV

Maybe I solved this (maybe I didn't) but wanted to post findings just in case someone else runs into them.

Also changed Place from "Tower Geeks" to "MQX Software Solutions" since it appears more to do with the default MQX 4.0 PSP code for the MCF5441x.

In init_hw.c, MQX 4.0 changes the NAND clock from the default divide by 32 to a divide by 14.

If I return the NAND clock to the default, there are no NAND errors.

Why it worked without the secondary riser in place is unknown.  Perhaps having the third board and riser in place added enough capacitance or potential for interference.. I''m not really a hardware guy so can't really say.

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