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i.mx6 DDR3 read & write calibration

Question asked by weidong zhou on Jul 6, 2014
Latest reply on Jul 7, 2014 by Yuri Muhin

Does that mean we do not need to do strictly length match between DQS signal and it's corresponding byte lanes, since i.mx6 DDR controller already support read and write calibration? If not, what purpose for design of these kind of calibration ?

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