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DDR memory hanging issue in K70 tower board

Question asked by PRAMOD K. G. on Jul 2, 2014
Latest reply on Jul 4, 2014 by Radek Sestak

Hi all,

 

                                         l am using the DDR memory of twr module for storing my high speed acquisition data. Currently  I am building my project as SRAM debug and DDR is enable when necessary. So i have two functions to enable and disable DDR ( code attached below ) . Now i can enable and disable DDR at run time, but my issue is that ddr gets hang after doing some number of these enabling and disabling. Please let me know some where i went wrong. I am attaching my the functions to enabling and disabling the ddr.

 

 

Thanks,

Pramod.

 

/*FUNCTION*---------------------------------------------------------------------

*

* Function Name    : ddr_enable

* Returned Value   :

* Comments         : DDRAM Enabling routine.

*

*END*-------------------------------------------------------------------------*/

 

void ddr_enable(void)

{

    SIM_MemMapPtr   sim = SIM_BASE_PTR;

    DDR_MemMapPtr   ddr = DDR_BASE_PTR;

    MCM_MemMapPtr   mcm = MCM_BASE_PTR;

 

    /* Enable DDR controller clock */

    sim->SCGC3 |= SIM_SCGC3_DDR_MASK;

   

    /* Enable DDR pads and set slew rate */

    sim->MCR |= 0xC4;   /* bits were left out of the manual so there isn't a macro right now */

 

    ddr->RCR |= DDR_RCR_RST_MASK;

 

    * (vuint_32 *)(0x400Ae1ac) = 0x01030203;

 

    /* TC's init */

    ddr->CR00 = 0x00000400;

    ddr->CR02 = 0x02000031;

    ddr->CR03 = 0x02020506;

    ddr->CR04 = 0x06090202;

    ddr->CR05 = 0x02020302;

    ddr->CR06 = 0x02904002;

    ddr->CR07 = 0x01000303;

    ddr->CR08 = 0x05030201;

    ddr->CR09 = 0x020000c8;

    ddr->CR10 = 0x03003207;

    ddr->CR11 = 0x01000000;

    ddr->CR12 = 0x04920031;

    ddr->CR13 = 0x00000005;

    ddr->CR14 = 0x00C80002;

    ddr->CR15 = 0x00000032;

    ddr->CR16 = 0x00000001;

    ddr->CR20 = 0x00030300;

    ddr->CR21 = 0x00040232;

    ddr->CR22 = 0x00000000;

    ddr->CR23 = 0x00040302;

    ddr->CR25 = 0x0A010201;

    ddr->CR26 = 0x0101FFFF;

    ddr->CR27 = 0x01010101;

    ddr->CR28 = 0x00000003;

    ddr->CR29 = 0x00000000;

    ddr->CR30 = 0x00000001;

    ddr->CR34 = 0x02020101;

    ddr->CR36 = 0x01010201;

    ddr->CR37 = 0x00000200;

    ddr->CR38 = 0x00200000;

    ddr->CR39 = 0x01010020;

    ddr->CR40 = 0x00002000;

    ddr->CR41 = 0x01010020;

    ddr->CR42 = 0x00002000;

    ddr->CR43 = 0x01010020;

    ddr->CR44 = 0x00000000;

    ddr->CR45 = 0x03030303;

    ddr->CR46 = 0x02006401;

    ddr->CR47 = 0x01020202;

    ddr->CR48 = 0x01010064;

    ddr->CR49 = 0x00020101;

    ddr->CR50 = 0x00000064;

    ddr->CR52 = 0x02000602;

    ddr->CR53 = 0x03c80000;

    ddr->CR53 = 0x03c803c8;

    ddr->CR53 = 0x03c803c8;

    ddr->CR56 = 0x020303c8;

    ddr->CR57 = 0x01010002;

 

    _ASM_NOP();

 

    ddr->CR00 |= 0x00000001;

 

    while ((ddr->CR30 & 0x400) != 0x400) {

    }

 

    mcm->CR |= MCM_CR_DDRSIZE(1); 

}

 

 

 

/*FUNCTION*---------------------------------------------------------------------

*

* Function Name    : ddr_disable

* Returned Value   :

* Comments         : DDRAM Disabling routine.

*

*END*-------------------------------------------------------------------------*/

 

void ddr_disable(void)

{   

   

    SIM_MemMapPtr   sim = SIM_BASE_PTR;

    DDR_MemMapPtr   ddr = DDR_BASE_PTR;

   

//    ddr->RCR |= DDR_RCR_RST_MASK;

   

    /* Enable DDR pads and set slew rate */

    sim->MCR   &= ~0xC4;   /* bits were left out of the manual so there isn't a macro right now */

   

    /* Enable DDR controller clock */

    sim->SCGC3 &= ~SIM_SCGC3_DDR_MASK;

 

}

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