I know that the Data Sheet for the iMX6SL says that the minimum voltage for the VDD_ARM_IN rail is 0.95V @ 400MHz but I am concerned about using this value with the PF0100 due to voltage ripple. My question is, what is the minimum SAFE value of VDD_ARM_IN when supplying the rail from an external PF0100 PMIC (with a +- 25mV accuracy and 10mV ripple)?
The reason for my confusion is that the on-chip PMU says that it provides ripple-rejection and I want to make sure I am interpreting the data sheet correctly, since I am bypassing the internal LDOs to save power. I am concerned that I will not save much power after all if I have to bump up the SW1AB voltage on the PF0100 to account for ripple and ensure proper operation across temperature, so I would like to keep it at 0.95V if it is safe.
Want to ensure this mode will operate correctly across temperature and process variance:
iMX6SL @ 400 MHz, Internal PMU: VDD_ARM_IN = internal bypass mode (TARG=0x1F)
PF0100 SW1AB connected to VDD_ARM_IN; Configured via SPI to 0.95V with boot code