Hi All
I have used RAppID to generate start-up and initialisation code for my demo board which is working.
As part of that I have setup a PWM signal on the EMIOS channel 0 and the code is shown below.
The system clock is 40 MHz and the global prescaler is set to 40 to give a 1MHz prescaler frequency.
I would like the PWM to be a 400uS pulse at a 1KHz rate.
The actual output is a 400uS pulse every 16 seconds.
The internal counter is 24 bit so 16 seconds is just the counter wrapping.
Can any one tell me how to set up the channel to give the required PWM.
Thanks
/*---------------------------------------------------------------------------------*/
/* EMIOS Module Configuration Register (EMIOS_MCR) */
/*---------------------------------------------------------------------------------*/
EMIOS.MCR.R = 0x14002700;
/* Module : Enable */
/* Global Freeze: Disabled */
/* Global Time Base Enable: Yes */
/* External Time Base: Unified Channel 23 */
/* Global Prescaler Enable: Yes */
/* Server Time slot: 0 */
/* Global Prescaler Value: 40 */
/* ----------------------------------------------------------- */
/* EMIOS Output Update Disable Register (EMIOS_OUDR) */
/* ----------------------------------------------------------- */
EMIOS.OUDR.R = 0x00000000;
/* Channel n output is Enabled */
/* n = 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 */
/* ----------------------------------------------------------- */
/* EMIOS Channel Disable Register (EMIOS_UCDIS) */
/* ----------------------------------------------------------- */
EMIOS.UCDIS.R = 0x00000000;
/* Channel n is Enabled */
/* n = 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23, */
/*---------------------------------------------------------------------------------*/
/* Unified Channel 00 Registers */
/*---------------------------------------------------------------------------------*/
EMIOS.CH[0].CADR.R = 0x00000258;
/* [0-23] Channel eMIOS_CADR0 Data Register - eMIOS_CADR0 : Value = 600*/
EMIOS.CH[0].CBDR.R = 0x000003E8;
/* [0-23] Channel eMIOS_CBDR0 Data Register - eMIOS_CBDR0 : Value = 1000*/
EMIOS.CH[0].CCR.R = 0x030006E0;
/* Channel Control Register */
/* Freeze Enable : Normal operation */
/* Output Disable : No */
/* Output Disable Select : ODI 0 */
/* Prescaler Divide Ratio : 1 */
/* Prescaler Enable : Enable */
/* DMA Memory access: Assigned to DMA */
/* Input Filter: Not Applicable */
/* Filter clock select : Prescaler clock */
/* Flag Enable : IRQ/DMA not generated */
/* Force Match A : Disabled */
/* Force Match B : Disabled */
/* Bus Select : Internal counter */
/* Edge Selection Bit :Not Applicable */
/* Edge Polarity :Set on Match A */
/* Mode : Output Pulse Width Modulation Buffered (flag on B1 match) */
