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[P2020]Problem of linking failed in P2020 36Bit setting based on SDKv1.3

Question asked by Wed Chen on Jun 27, 2014
Latest reply on Jul 7, 2014 by Min Zhao

Hello all,

 

    we have a stable P2020 u-boot environment based on FreeScale SDK v1.3.

 

In 32-bit mode, we could compile and make bootloader bin file successfully.

 

Now, for requirement of support 4G DDR and that means we need to support 36-bit physical address access.

 

After refer to P2020RDB_PC settings, we have following modifications:

 

1. Modify P2020.config to support 36BIT access, and we make sure 'CONFIG_36BIT' is set correctlly.

2. Modify p2020.h

#define CONFIG_SYS_TEXT_BASE 0xe3f40000

#define CONFIG_RESET_VECTOR_ADDRESS 0xe3ffffff

#define CONFIG_SYS_CCSRBAR 0xffe00000

#define CONFIG_SYS_FLASH_BASE 0xfe0000000ull

#define CONFIG_SYS_PCIE1_MEM_VIRT 0xf90000000ull

#define CONFIG_SYS_PCIE1_IO_VIRT 0xfffc30000ull

#define CONFIG_SYS_CPLD_BASE 0xfea000000ull

#define CONFIG_SYS_NAND_BASE 0xffff00000ull

 

However, we met below link error messages :

/home/ithinkchen/SWITCH/Urus2_4G/output/host/usr/powerpc-buildroot-linux-gnu/sysroot/usr/lib/powerpc-fsl-linux-gnuspe/4.6.2 -lgcc -Map u-boot.map -o u-boot

/home/ithinkchen/SWITCH/Urus2_4G/output/host/usr/bin/powerpc-fsl-linux-gnuspe-ld:u-boot.lds:1: ignoring invalid character `#' in expression

/home/ithinkchen/SWITCH/Urus2_4G/output/host/usr/bin/powerpc-fsl-linux-gnuspe-ld:u-boot.lds:1: syntax error

 

Can any one give use some clues about this link error?

 

We didn't touch/modify the file u-boot.lds in arch/powerpc/cpu/mpc85xx/.

 

============================================================================

 

#include "config.h" /* CONFIG_BOARDDIR */

 

 

#ifdef CONFIG_RESET_VECTOR_ADDRESS

#define RESET_VECTOR_ADDRESS CONFIG_RESET_VECTOR_ADDRESS

#else

#define RESET_VECTOR_ADDRESS 0xfffffffc

#endif

 

 

OUTPUT_ARCH(powerpc)

 

 

PHDRS

{

  text PT_LOAD;

  bss PT_LOAD;

}

 

 

SECTIONS

{

  /* Read-only sections, merged into text segment: */

  . = + SIZEOF_HEADERS;

  .interp : { *(.interp) }

  .text      :

  {

    *(.text*)

   } :text

    _etext = .;

    PROVIDE (etext = .);

    .rodata    :

   {

    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))

  } :text

 

 

  /* Read-write section, merged into data segment: */

  . = (. + 0x00FF) & 0xFFFFFF00;

  _erotext = .;

  PROVIDE (erotext = .);

  .reloc   :

  {

    _GOT2_TABLE_ = .;

    KEEP(*(.got2))

    KEEP(*(.got))

    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);

    _FIXUP_TABLE_ = .;

    KEEP(*(.fixup))

  }

  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;

  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;

 

 

  .data    :

  {

    *(.data*)

    *(.sdata*)

  }

  _edata  =  .;

  PROVIDE (edata = .);

 

 

  . = .;

  __u_boot_cmd_start = .;

  .u_boot_cmd : { *(.u_boot_cmd) }

  __u_boot_cmd_end = .;

 

 

  . = .;

  __start___ex_table = .;

  __ex_table : { *(__ex_table) }

  __stop___ex_table = .;

 

 

  . = ALIGN(256);

  __init_begin = .;

  .text.init : { *(.text.init) }

  .data.init : { *(.data.init) }

  . = ALIGN(256);

  __init_end = .;

 

 

  .bootpg RESET_VECTOR_ADDRESS - 0xffc :

  {

    arch/powerpc/cpu/mpc85xx/start.o (.bootpg)

  } :text = 0xffff

 

 

  .resetvec RESET_VECTOR_ADDRESS :

  {

    KEEP(*(.resetvec))

  } :text = 0xffff

 

 

  . = RESET_VECTOR_ADDRESS + 0x4;

 

 

  /*

   * Make sure that the bss segment isn't linked at 0x0, otherwise its

   * address won't be updated during relocation fixups.  Note that

   * this is a temporary fix.  Code to dynamically the fixup the bss

   * location will be added in the future.  When the bss relocation

   * fixup code is present this workaround should be removed.

   */

#if (RESET_VECTOR_ADDRESS == 0xfffffffc)

  . |= 0x10;

#endif

 

 

  __bss_start = .;

  .bss (NOLOAD)       :

  {

   *(.sbss*)

   *(.bss*)

   *(COMMON)

  } :bss

 

 

  . = ALIGN(4);

  __bss_end__ = . ;

  PROVIDE (end = .);

}

 

 

With best regards,

Wed.

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