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Flex timer initialization for pwm generation on k53 is not working

Question asked by renganathan bs on Jun 21, 2014
Latest reply on Mar 23, 2015 by Nitin Harish

I wish to use the Flex timer for generating PWM signals and porting it to one of the port to control the intensity of the LED. This is the code which I have done till now and tried to generate edge aligned pwm with 50% duty cycle. I am currently using k53 tower board. Problem is that it is TOF flag is not getting set and it is not going to the ISR. Checking step up step with the registers I was able to find out the CNT register is not updating once it leaves this ftm0_init() function and goes into infinite while loop.

 

CODE :

 

void ftm0_init()

{

  SIM_SCGC6 |=SIM_SCGC6_FTM0_MASK; //TURN ON FTM0 TIMER

  FTM0_MODE = ( (FTM_MODE_WPDIS_MASK & 0x01) | (FTM_MODE_FTMEN_MASK & 0x01)); /* enabling write protection and file access */

  // disabling ftm0

  FTM0_SC = (FTM_SC_CLKS(0x00) | FTM_SC_PS(0x00));

  FTM0_PWMLOAD |= FTM_PWMLOAD_LDOK_MASK|FTM_PWMLOAD_CH1SEL_MASK;

  //FTM0_MODE = ( (FTM_MODE_WPDIS_MASK & 0x00) | (FTM_MODE_FTMEN_MASK & 0x00)); /* enabling write protection and file access */

  FTM0_CNTIN = FTM_CNTIN_INIT(0x00);

  FTM0_CNT = FTM_CNT_COUNT(0x00);

  FTM0_MOD = FTM_MOD_MOD(0x32);

  FTM0_C1SC = (FTM_CnSC_MSB_MASK | (FTM_CnSC_ELSB_MASK) | (FTM_CnSC_ELSA_MASK & 0x00)); /* Set up channel status and control register */

  FTM0_C1V = FTM_CnV_VAL(0x19);        /* Set up channel value register */

  FTM0_PWMLOAD |= FTM_PWMLOAD_LDOK_MASK|FTM_PWMLOAD_CH1SEL_MASK;

  FTM0_STATUS |= (FTM_STATUS_CH1F_MASK & 0x00);

  FTM0_CONF |= (FTM_CONF_NUMTOF_MASK & 0x00);

  disable_irq(62);

  __VECTOR_RAM[78]=(uint32)ftm0_isr;

enable_irq(62); //FTM2 Vector is 80. IRQ# is 80-16=64

  //enabling ftm0

  FTM0_SC = FTM_SC_TOIE_MASK|(FTM_SC_CLKS(0x01) | FTM_SC_PS(0x00));

  FTM0_MODE = ( (FTM_MODE_WPDIS_MASK & 0x00) | (FTM_MODE_FTMEN_MASK & 0x00)); /* enabling write protection and file access */

 

  SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;

  PORTA_PCR11 = PORT_PCR_MUX(3);

  GPIOA_PDDR = 0xFFFFFFFF;

}

void main (void)

{

  ftm0_init();

  while(1);

}

void ftm0_isr()

{

   FTM0_MODE = ( (FTM_MODE_WPDIS_MASK & 0x01) | (FTM_MODE_FTMEN_MASK & 0x01)); /* enabling write protection and file access */

  // disabling ftm0

  FTM0_SC = (FTM_SC_CLKS(0x00) | FTM_SC_PS(0x00));

  FTM0_CNTIN = FTM_CNTIN_INIT(0x00);

  FTM0_CNT = FTM_CNT_COUNT(0x00);

  FTM0_MOD = FTM_MOD_MOD(0x32);

  FTM2_C1V = FTM_CnV_VAL(0x19);        /* Set up channel value register */

  FTM0_PWMLOAD |= FTM_PWMLOAD_LDOK_MASK|FTM_PWMLOAD_CH1SEL_MASK;

  FTM0_STATUS |= (FTM_STATUS_CH1F_MASK & 0x00);

  FTM0_CONF |= (FTM_CONF_NUMTOF_MASK & 0x00);

  FTM0_SC |= (FTM_SC_TOF_MASK & 0x00);

  //enabling ftm0

  FTM0_SC = (FTM_SC_CLKS(0x01) | FTM_SC_PS(0x00));

  FTM0_MODE = ( (FTM_MODE_WPDIS_MASK & 0x00) | (FTM_MODE_FTMEN_MASK & 0x00)); /* enabling write protection and file access */

}

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