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ADC EOSI Delay not as expected (MC56F82726)

Question asked by mätthu on Jun 19, 2014
Latest reply on Jul 9, 2014 by Matthias Uhlmann

Hi All,

 

I trigger my ADC with PWM-Trigger and sample 4 samples (ANA0,ANA3,ANB0,ANB3) in parallel mode, but the EndOfScanInterrupt occurs to late (3.2us instead of 1.8us)

- Clock divider is correct (50MHz / 5 = 10MHz)          => ADC_CTRL2[DIV] = 5;

- No Automatic Standby or Power Down enabled      => ADC_PWR[ASB] = 0; ADC_PWR[APD] = 0;

 

It looks like the ADC need to power up each time (delayed ~1.4us => Power up delay = 1.3us) and I can not see any differences when I enable ADC_PWR[ASB] or ADC_PWR[APD]...

 

I have no Idea what is wrong initialised.

 

Regards

Matthias

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