I am trying to use MX53_PAD_CSI0_MCLK as clock source for aptina MT9p031. And configure CSI0 to gated mode so I don't need HSYNC input.
And I already inserted the macro "MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK," to mx53_loco.c.
However I still can not get clock output.
Anyone could advise?
Thanks a lot.
Solved! Go to Solution.
I think you can add in mx53_loco.c
code to program CCM_CSCDR4 and IPOMUX register
directly using __raw_writew().
Best regards
chip
Hi Weiqiang
please try in mx53_loco.c in structure iomux_v3_cfg_t mx53_loco_pads[]
to replace MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC,
with MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK
Best regards
chip
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Actually that is what I already did.
I still can not get MCLK out from that pin.
Any idea?
Thanks.
I think you can add in mx53_loco.c
code to program CCM_CSCDR4 and IPOMUX register
directly using __raw_writew().
Best regards
chip