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Please review our DDR connection with imx23

Question asked by jlumme on Jun 18, 2014
Latest reply on Jun 23, 2014 by jlumme

In our last build we had big issues with DDR stability in our prototype, basically because of inexperience of designing this type of memory connections.

We managed to get it working with halving the CPU speed, and loosening the timings slightly, but for our next version, we are trying to make it work 100%.

We made several mistakes last time:

- routed some of the data lines through 3 layers, and some from 2.

- did not match the line lengths

- our capacitor placement for memory power lines was not as close to the chip as possible.

 

This time we have fixed those mistakes, but would still like to hear some feedback from experienced designers.

Sorry in advance already for adding several pictures, and in PADS it's impossible (to my knowledge) to color different layers differently when wire is "selected", so it might be little bit difficult to figure out the lines. I.mx is on the right, and DDR on the left.

 

So first of all, this time we have routed the clock lines as differentials, and they look like this:

clk.jpg

 

We have routed our data lines all through only 2 layers (couple of them go through the power plane, we couldn't avoid it), and trace lengths are matched as close as possible. So the amount of VIAs is same on every trace:

data2.png

Our address lines are also all going through 2 layers, and trace lengths are matched as close as possible:

address2.png

Our capacitors for the power lines of DDR memory, are all placed as close to the chip as possible:

caps.jpg

 

Our trace lengths are currently:

CS 18.8

CLNK 30.1

CLK 30.4

CKE 36.1

A0 37.2

A1 37.2

A2 27.2

A3 37.2

A4 36.2

A5 36.1

A6 36.2

A7 36.2

A8 36.2

A9 36.2

A10 37.2

A11 36.2

A12 36.2

D0 35.5

D1 35.6

D2 36.2

D3 36.2

D4 27.3

D5 36.2

D6 36.1

D7 36.2

D8 37.2

D9 36

D10 28

D11 36.1

D12 36.1

DQM0 36.1

DQM1 36.2

DQS0 35.6

DQS1 37.2

CASN 37.2

RASN 37.2

BA0 37.2

BA1 37.2

WEN 36.1

 

We matched also CASN and RASN lengths. Our CS is much shorter than other lines, but we are assuming this woudln't be a problem..

So, please we could use some advice and tips where we might have gone wrong...

 

Edit: Replaced the data and address line images with edited images that are much easier to read

 

Thanks!

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