In our last build we had big issues with DDR stability in our prototype, basically because of inexperience of designing this type of memory connections.
We managed to get it working with halving the CPU speed, and loosening the timings slightly, but for our next version, we are trying to make it work 100%.
We made several mistakes last time:
- routed some of the data lines through 3 layers, and some from 2.
- did not match the line lengths
- our capacitor placement for memory power lines was not as close to the chip as possible.
This time we have fixed those mistakes, but would still like to hear some feedback from experienced designers.
Sorry in advance already for adding several pictures, and in PADS it's impossible (to my knowledge) to color different layers differently when wire is "selected", so it might be little bit difficult to figure out the lines. I.mx is on the right, and DDR on the left.
So first of all, this time we have routed the clock lines as differentials, and they look like this:
We have routed our data lines all through only 2 layers (couple of them go through the power plane, we couldn't avoid it), and trace lengths are matched as close as possible. So the amount of VIAs is same on every trace:
Our address lines are also all going through 2 layers, and trace lengths are matched as close as possible:
Our capacitors for the power lines of DDR memory, are all placed as close to the chip as possible:
Our trace lengths are currently:
We matched also CASN and RASN lengths. Our CS is much shorter than other lines, but we are assuming this woudln't be a problem..
So, please we could use some advice and tips where we might have gone wrong...
Edit: Replaced the data and address line images with edited images that are much easier to read