I noticed that the iMX6 cache prefetching is disabled, and then found the erratum on that topic, saying that enabling prefeching can lead to deadlock or data corruption.
My questions are -
1. I want to enable prefetching, to see how often my application will suffer from this issue. How can I do that? (I'm using iMX6Q running u-boot 2009 and linux 3.0.35_4.1)
I found the ARM documentation regarding ACTLR register (ARM Information Center) but couldn't find the right place to update this value in the u-boot / kernel.
2. When doing some profiling on my DDR I see a big difference between reads and writes - DDR write is more or less x8 faster than reads. Assuming that data prefetching is disabled - does this difference make sense?
The profiler is doing continuous block reading/writing for blocks larger than the L2 cache.