I've ported over a simple kernel module from here (i.MX51 EIM bus clarified) and ported it to the imx6 and am doing a simple read of one address location on the EIM bus. When reading this one location, I get two chip select cycles going low, even though the data is only shown on the first chip select cycle. Why am I seeing two chip selects (and two Address strobe and two RWN cycles going low)? I don't see an example of this in any of the timing diagram. Note: I am able to confirm that I can read what I have written so I think the bus is working in terms of data writes and reads. Its just the double chip select cycles going low that is bothering me.
P.S. In the screenshot MX6_DAT_IN(1) is really the EIM BCLK