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I am trying to debug DDR3 issues on a new hardware design.

Question asked by Bob Simning on Jun 11, 2014
Latest reply on Jun 19, 2014 by Bob Simning

I am trying to debug DDR3 issues on a new hardware design. I would like to slow the DDR accesses to help distinguish between layout and timing issues. I had hoped I could change the ARM_CLK_DIV parameter in the CCM_CACCR register. However, if I change the value from the current setting (0) to anything else, any read/write access to DDR address space “hang”. Any ideas what I'm missing?

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