I am trying to debug DDR3 issues on a new hardware design. I would like to slow the DDR accesses to help distinguish between layout and timing issues. I had hoped I could change the ARM_CLK_DIV parameter in the CCM_CACCR register. However, if I change the value from the current setting (0) to anything else, any read/write access to DDR address space “hang”. Any ideas what I'm missing?