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How can i get the 28MHZ ldb_di0_clk

Question asked by king liu on Jun 10, 2014
Latest reply on Jun 24, 2014 by igor ferrara

I want to connect the imx6 to a lvds panel .The lcd need the 28MHZ pixclock.

But no matter what how I set the static struct fb_videomode ldb_modedb[] table .

the ldb_di0_clk always is 38MHZ.


I find the reason:

The ldb_di0_clk romaps is 

        pll2_528_bus_main_clk  ->  pll2_pfd_352M  ->  ldb_di0_clk

The  range of divisor form pll2_528_bus_main_clk  to pll2_pfd_352M is 12-35.

Refer to the IMX6DQRM.pdf CCM_ANALOG_PFD_528n

29–24 PFD3_FRAC  This field controls the fractional divide value. The resulting frequency shall be 528*18/PFD3_FRAC where

                                   PFD3_FRAC is in the range 12-35.

528M *18 /35 = 271M


The  range of divisor form  pll2_pfd_352M  to ldb_di0_clk is only 3.5 or 7.

Refer to the IMX6DQRM.pdf  CCM_CSCMR2

ldb_di0_ipu_div Control for divider of ldb clock for IPU di0 0 divide by 3.5  1 divide by 7(default)

271M /7 =38M

So  if i want to generate the 28M clk,

Can i  change the ldb_dio_clk romap?

How to do it?