Memory assignment in Codewarrior(v10.3.3)

[敏赵]

Hello there,

I an designing a product using p2020cpu refering to the design of p2020rdb-pc. I have 4GB DDR, 32MB Nor Flash and no PCI. So I have to modify the memory map.In 36-bit u-boot my memory map:

                               0x0_0000_0000  0x0_ffff_ffff   DDR

                               0x1_e000_0000  0x1_e00f_ffff  CCSRBAR                                            

                               0xf_fe00_0000   0xf_ffff_ffff     NOR  (0xf_eff8_0000 uboot)

I already have the appropriate 36-bit u-boot, I want to download the .bin file to my board.

I have some questions:

(1)Can I assign the address as above? Can I assign the NOR base address as I want?

(2)Do the memory windows in the Codewarrior have relationship with the memory map in u-boot? Or I can assign the address as I want?

(3)How should I assign the memory windows in Codewarrior?

(4)How should I build a project to achieve my memory map？

The steps that I download a 32-bit u-boot to p2020rdb-pc in Codewarrior is:file>new>codewarrior bareboard project  wizard>board-p2020rdb-pc >others is default.In Target Task I set Target RAM 00002000-00030000,Base Address FF000000.

(5)Now should I also choose p2020rdb-pc board? How can I achieve the 36-bit?

(6)Should I modify the files such as p2020rdb-pc_init_core.tcl? How to modify it?

Best regards,

Min Zhao

[yipingwang]

1. Please refer to the attached 36bit u-boot memory map for P2020RDB-PC from Linux SDK document.

2. CodeWarrior memory map defined in the initialization file PA\PA_Support\Initialization_Files\QorIQ_P2\P2020RDB-PC_init_core.tcl doesn't have relationship with u-boot.

3. Please modify the initialization file P2020RDB-PC_init_core.tcl according to your target, please pay attention to LAW and MMU initialization sections.

4. You could use the same  CodeWarrior project to flash 36 bit u-boot as 32 bit u-boot.

5. The  CodeWarrior bare board project doesn't have relationship with u-boot, please don't make them confused.

6. The initialization file P2020RDB-PC_init_core.tcl is designed for P2020RDB-PC demo board, you need to modify it according to your target board.

Have a great day,
Yiping Wang

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[敏赵]

In p2020RDB-PC_init_core.tcl, I find the codes:

##################################################################################

1. Memory Windows

#

1. 0xFF000000 0xFFFFFFFF LAW0 Local Bus NOR FLASH - 16M

1. 0xA0000000 0xBFFFFFFF LAW1 PEX1 - 512M

1. 0xEFC20000 0xEFC2FFFF LAW2 PEX1 - 64K

1. 0x80000000 0x9FFFFFFF LAW3 PEX2 - 512M

1. 0xEFC10000 0xEFC1FFFF LAW4 PEX2 - 64K

#0xF8000000 0xF80FFFFF LAW5 Local Bus NAND FLASH 1M

1. 0x00000000 0x3FFFFFFF LAW11 DDRC - 1G

#

##################################################################################

1. configure local access windows

1. LAWBAR0 - Local Bus

1. bit 8 - 31 = 0xFF000000 - base addr

mem = 0x000ff000

##################################################################################

In my board,I have a 4GB DDR,32MB NOR, so I must use 36-bit address.

How should I set the Registers? I found they only can use 32-bit?

For example my NOR's base address is 0xF_FE000000,

then mem = ?

PS: can I send message to you with Chinese

Best regards,

Min Zhao

[yipingwang]

I forgot to mention just now, if you only want to flash u-boot, you could use the initialization file P2020RDB-PC_init_sram_flash.tcl to avoid to configure DDR(controller). Please adjust Memory allocation for NOR Flash according to your target(LAW memory Window and MMU memory sections).

It's better to use English, because we could share these information with others, please feel free to post anything unclear.

Have a great day,
Yiping Wang

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[敏赵]

In In p2020RDB-PC_init_core.tcl

First it define： variable CCSRBAR 0xff700000

Then: 

# move CCSR at 0xE0000000

		# CCSRBAR
		# bit 8 - 23 - BASE_ADDR
		mem [CCSR 0x0] = 0x000e0000
		set CCSRBAR 0xe0000000

Why define  variable CCSRBAR 0xff700000?

Best regards,

Min Zhao

[yipingwang]

For QorIQ processors, the default CCSBAR is 0xff700000, this address overlaps with NOR Flash Window from 0xFF000000 to 0xFFFFFFFF, so it is needed to change CCSBAR to other address(0xe0000000).

Have a great day,
Yiping Wang

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[敏赵]

In my board,DDR's address is 0x00000000 ~0x ffffffff, NOR's address is 0xf_fe000000 ~0xf_ffffffff. So I should modify the LAW configuration.

# configure local access windows

	# LAWBAR0 - Local Bus
	# bit 8 - 31 = 0xF_FE000000 - base addr
	mem [CCSR 0xc08] = 0x00ffe000

Then what figure should I assign to CCSR at the beginging? Or I needn't to modify it?

variable CCSRBAR  ?

What's more I found

	# Set a breakpoint at the reset address
	reg ${SPR_GROUP}IAC1 = 0xfffffffc

Then reg ${SPR_GROUP}IAC1 = ?

Best regards,

Min Zhao

[yipingwang]

For flashing u-boot, I suggest you use the initialization file P2020RDB-PC_init_sram_flash.tcl, and the flash programmer algorithm will run on SRAM.

Please pay attention to the following configuration for NOR Flash.

	# LAWBAR0 - Local Bus

  # bit 8 - 31 = 0xFF000000 - base addr

    mem [CCSR 0xc08] = 0x000ff000

# define 16MB  TLB1 entry 2: 0xFF000000 - 0xFFFFFFFF; for Local Bus, cache inhibited

reg ${CAM_GROUP}L2MMU_CAM2  = 0x70000FCAFC080000FF000000FF000001

Change these configurations for your target.

  mem [CCSR 0xc08] = 0x000fe000

reg ${CAM_GROUP}L2MMU_CAM2  = 0x70000FCAFC080000FE000000FE000001

No need to touch other core related configurations, for example CCSRBAR or IAC1.

Have a great day,
Yiping Wang

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[敏赵]

Because my DDR is 4G. So my memory windows is 0x00000000 ~0xffffffff  LAW11 DDR

Then can I  mem [CCSR 0xc08] = 0x000fe000 ? Can the memory windows work?

Other people tell me I should

mem [CCSR 0xc08] = 0x00ffe000,

but in this situation I don't konw how to assign the reg ${CAM_GROUP}L2MMU_CAM2

Do you mean I see the nor's base address as fe000000?

Best regards,

Min Zhao

[yipingwang]

I mean the 32M NOR Flash is from fe000000 to ffffffff.

I know the reason why you want to use 36bit address space, because your purpose is only want to use CodeWarrior to flash u-boot image(32bit or 36bit) to NOR Flash. so I have two options for you.

1. Use P2020RDB-PC_init_sram_flash.tcl, no need to care about DDR at all.

2. Modify p2020rdb-pc_init_core.tcl to map and use part of DDR memory(for example 1G), but I don't suggest this way, because probably you also need to configure DDR controller setting parameters to make it suitable for  your new DDR.

Have a great day,
Yiping Wang

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[敏赵]

Do you mean I only need to modify these configurations

  mem [CCSR 0xc08] = 0x000fe000

reg ${CAM_GROUP}L2MMU_CAM2  = 0x70000FCAFC080000FE000000FE000001

And the size of DDR in LAW needn't match to 4G.

Best regards,

Min Zhao

[yipingwang]

The processor only can access 4G memory space at the same time, and MMU is used to extend the physical address.

The physical address of NOR flash is 0xf_fe00_0000

mem [CCSR 0xc08] = 0x00ffe000

reg ${CAM_GROUP}L2MMU_CAM2  = 0x0F7000CAFC08000FFE00000FE000001

And no need to map DDR in SRAM initialization file.

Have a great day,
Yiping Wang

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[敏赵]

(1)How should I enable the MAS7?

(2) My NAND is 1GB.  How much the size should I assign to it in codewarrior? 1M?

(3)Do I modify the following codes?

# boot from nor gpcm 16 bit boot location (default)

# CS0 - NOR Flash

# BR0 base address at 0xFF000000, port size 16 bit, GPCM, DECC disabled

mem [CCSR 0x5000] = 0xFF001001 -----------> mem [CCSR 0x5000] = ?

Best regards,

Min Zhao

[yipingwang]

(1) Define 36 bit physical address page in TLB entry.

(2) NAND Flash is not memory mapped, it is needed to map the internal SRAM within NAND Flash.

(3) Yes, I attached an application note for you.

Have a great day,
Yiping Wang

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[敏赵]

(2)In p2020rdb-pc, NAND is 32MB, and it's assigned 1MB in LAW in codewarrior.

I want to know now my NAND is 1GB, should I still assign 1M?

(3)My BR0 base address at 0xFE000000? And does it mean when I download the bin file to my board, the base address is fe000000 not ffe000000 in target task?

Best regards,

Min Zhao

[yipingwang]

(2) Yes, 1M is enough.

(3) Fe000000 is effective address, in CodeWarrior IDE or programs you need to use effective addresses.

In addition, about BR0 definition, please refer to "5.16.1 Base Register (BR0–BR7)" in the app note AN3366.

Have a great day,
Yiping Wang

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[敏赵]

You gave me one option to use P2020RDB-PC_init_sram_flash.tcl. But my cw project only contains P2020RDB-PC_init_core.tcl and P2020RDB-PC_init_rom.tcl

Best regards,

Min Zhao

[yipingwang]

About this topic, I need to explain more, it is possible to use P2020RDB-PC_init_sram_flash.tcl to initialize your customized board and flash 36 bit u-boot onto the flash, only with the modification for 64M NOR Flash. This initialization file uses L2 as SRAM, so no need to consider about 4G DDR in the physical memory map.

Please note,the effective address used by a process is translated into a physical address by the processor’s MMU. The physical address goes out on the bus and is matched against the LAWs(defined by users) to determine which device should respond to the transaction.

Have a great day,
Yiping Wang

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[yipingwang · Accepted solution]

CodeWarrior 10.3.3 contains this initialization file in the folder CW_PA_v10.3.3\PA\PA_Support\Initialization_Files\QorIQ_P2.

I attached it for you.

Have a great day,
Yiping Wang

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