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To find the root cause of i.MX6Q IPU error interrupt.

Question asked by Satoshi Shimoda on Jun 8, 2014
Latest reply on Jun 16, 2014 by igorpadykov

Hi community,

 

I have a question about i.MX6Q IPU.

Please see Table 37-35 in IMX6DQRM Rev.1.

Sometimes IPU_INT_STAT5[0] and IPU_INT_STAT10[0] is occurred on a custom board.

These interrupts seem that these are generated by input data from CSI, so we checked whether input data from camera is over the i.MX6Q CSI spec, but the input data is smaller than the maximum spec of CSI sufficiently. (camera data: 1920x1080@30fps BT.1120)

And they have already set IPUx_HSP_CLK_ROOT to large value adequately (264MHz), so we think the root cause is not performance of CSI.

In this case, could you give me a advice what should we check to find root cause?

(e.g. we should check the signal integrity of camera data, IPU output IPU_INT_STAT5[0] or IPU_INT_STAT10[0] if memory bandwitdh is not sufficient, etc..)

 

For your information, IPU is used to output 320x240 10fps also.

 

Best Regards,

Satoshi Shimoda

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