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CAN with M4-Core

Question asked by Manuel Dürnberger on Jun 6, 2014
Latest reply on Jun 17, 2014 by Timesys Support

Hi!

 

I'm trying to make the FlexCAN-module work with the M4-core of my Cosmic+ Board running Phytec`s phyCORE-Vybrid.

The SoM's Freescale version number is:

PVF61GS151CMK50

Test REV C3

1N02G

XAA1308D

 

I know, that right now the FlexCAN-module is not supported by MQX/Linux (yet?). Are there any plans to support the CAN-module?

Using the Board within CAN-applications is one of the main reasons why I chose the Vybrid. That is why it is very important for me to make the CAN work...

 

So, what I did so far is trying to initialize the FlexCAN by accessing the corresponding registers "on my own".

Somehow the Vybrid is not able to leave the "Freeze Mode".

This is my function for init-process:

 

void can_init(void)
{
    struct CAN_MemMap *can0dev;
    can0dev = CAN0_BASE_PTR;
    /* initialization of CAN RX pinš*/
        /* initialization of CAN TX pin */
      /* CCM_CCGR2: CG8=2 */
      CCM_CCGR2 = (uint32_t)((CCM_CCGR2 & (uint32_t)~(uint32_t)(
                   CCM_CCGR2_CG8(0x01)
                  )) | (uint32_t)(
                   CCM_CCGR2_CG8(0x02)
                  ));
      /* IOMUXC_PTB14: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,MUX_MODE=1,??=0,??=0,??=0,??=0,??=0,??=0,OBE=0,IBE=0 */
      IOMUXC_PTB14 = (uint32_t)((IOMUXC_PTB14 & (uint32_t)~(uint32_t)(
                          IOMUXC_RGPIO_MUX_MODE(0x06) |
                      IOMUXC_RGPIO_OBE_MASK |
                      IOMUXC_RGPIO_IBE_MASK |
                      0xFF8FC000U
                     )) | (uint32_t)(
                     IOMUXC_RGPIO_MUX_MODE(0x01)
                     ));
      /* IOMUXC_PTB15: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,MUX_MODE=1,??=0,??=0,??=0,??=0,??=0,??=0,OBE=0,IBE=0 */
      IOMUXC_PTB15 = (uint32_t)((IOMUXC_PTB15 & (uint32_t)~(uint32_t)(
                          IOMUXC_RGPIO_MUX_MODE(0x06) |
                      IOMUXC_RGPIO_OBE_MASK |
                      IOMUXC_RGPIO_IBE_MASK |
                      0xFF8FC000U
                     )) | (uint32_t)(
                     IOMUXC_RGPIO_MUX_MODE(0x01)
                     ));

      CAN0_MCR |= CAN_MCR_MDIS_MASK;       /* Disable CAN module */
        /*XTAL Clock*/
        /* CAN0_CTRL1: PRESDIV=0,RJW=0,PSEG1=0,PSEG2=0,BOFFMSK=0,ERRMSK=0,CLKSRC=0,LPB=0,TWRNMSK=0,RWRNMSK=0,??=0,??=0,SMP=0,BOFFREC=0,TSYN=0,LBUF=0,LOM=0,PROPSEG=0 */
        CAN0_CTRL1 = CAN_CTRL1_PRESDIV(0x00) |
                     CAN_CTRL1_RJW(0x00) |
                     CAN_CTRL1_PSEG1(0x00) |
                     CAN_CTRL1_PSEG2(0x00) |
                     CAN_CTRL1_PROPSEG(0x00);
        /* CAN0_MCR: MDIS=0,SOFTRST=1 */
        CAN0_MCR = (uint32_t)((CAN0_MCR & (uint32_t)~(uint32_t)(
                    CAN_MCR_MDIS_MASK
                   )) | (uint32_t)(
                    CAN_MCR_SOFTRST_MASK
                   ));                       /* Soft Reset */
        while (CAN_PDD_GetSoftResetState(CAN0_BASE_PTR) == CAN_PDD_NOT_RESET){} /* Wait for Soft reset Acknowledge */
        while (CAN_PDD_GetFreezeAck(CAN0_BASE_PTR) == CAN_PDD_NOT_FREEZE){} /* Wait for entering the freeze mode */
        /* CAN0_MCR: WRNEN=1,SRXDIS=1,MAXMB&=~0x0E,MAXMB|=1 */
        CAN0_MCR = (uint32_t)((CAN0_MCR & (uint32_t)~(uint32_t)(
                    CAN_MCR_MAXMB(0x0E)
                   )) | (uint32_t)(
                    CAN_MCR_WRNEN_MASK |
                    CAN_MCR_SRXDIS_MASK |
                    CAN_MCR_MAXMB(0x01)
                   ));                       /* MCR reg. Settings */
        /* CAN0_CTRL1: PRESDIV|=5,PSEG1|=3,PSEG2|=1,BOFFMSK=1,ERRMSK=1,TWRNMSK=1,RWRNMSK=1,LBUF=1 */
        CAN0_CTRL1 |= CAN_CTRL1_PRESDIV(0x05) |
                      CAN_CTRL1_PSEG1(0x03) |
                      CAN_CTRL1_PSEG2(0x01) |
                      CAN_CTRL1_BOFFMSK_MASK |
                      CAN_CTRL1_ERRMSK_MASK |
                      CAN_CTRL1_TWRNMSK_MASK |
                      CAN_CTRL1_RWRNMSK_MASK |
                      CAN_CTRL1_LBUF_MASK;   /* Setting CTRL1 register */
        /* CAN0_CTRL2: RRS=1 */
        CAN0_CTRL2 |= CAN_CTRL2_RRS_MASK;    /* Setting CTRL2 register */
        /* CAN0_RXMGMASK: MG=0x1FFFFFFF */
        CAN0_RXMGMASK = CAN_RXMGMASK_MG(0x1FFFFFFF); /* Set the Global acceptance mask register */
        /* CAN0_RX14MASK: RX14M=0x1FFFFFFF */
        CAN0_RX14MASK = CAN_RX14MASK_RX14M(0x1FFFFFFF); /* Set the acceptance mask register for buffers 14 */
        /* CAN0_RX15MASK: RX15M=0x1FFFFFFF */
        CAN0_RX15MASK = CAN_RX15MASK_RX15M(0x1FFFFFFF); /* Set the acceptance mask register for buffers 15 */
        /* CAN0_MECR: ECRWRDIS=0 */
        CAN0_MECR &= (uint32_t)~(uint32_t)(CAN_MECR_ECRWRDIS_MASK); /* Enable writing into Memory error control register */
        /* CAN0_MECR: ECRWRDIS=1,ECCDIS=1 */
        CAN0_MECR |= (CAN_MECR_ECRWRDIS_MASK | CAN_MECR_ECCDIS_MASK); /* Disable memory error detection and correction */

        /* Initialize the message buffer 0 - Rx */
        /* CAN0_CS0: ??=0,??=0,??=0,??=0,CODE=4,??=0,SRR=0,IDE=0,RTR=0,DLC=0,TIME_STAMP=0 */
        CAN0_CS0 = (CAN_CS_CODE(0x04) | CAN_CS_DLC(0x00) | CAN_CS_TIME_STAMP(0x00));

        /* CAN0_ID0: PRIO=0,STD=0x07FF,EXT=0 */
        CAN0_ID0 = (CAN_ID_PRIO(0x00) | CAN_ID_STD(0x07FF) | CAN_ID_EXT(0x00));
        /* CAN0_WORD00: DATA_BYTE_0=0,DATA_BYTE_1=0,DATA_BYTE_2=0,DATA_BYTE_3=0 */
        CAN0_WORD00 = CAN_WORD0_DATA_BYTE_0(0x00) |
                      CAN_WORD0_DATA_BYTE_1(0x00) |
                      CAN_WORD0_DATA_BYTE_2(0x00) |
                      CAN_WORD0_DATA_BYTE_3(0x00);
        /* CAN0_WORD10: DATA_BYTE_4=0,DATA_BYTE_5=0,DATA_BYTE_6=0,DATA_BYTE_7=0 */
        CAN0_WORD10 = CAN_WORD1_DATA_BYTE_4(0x00) |
                      CAN_WORD1_DATA_BYTE_5(0x00) |
                      CAN_WORD1_DATA_BYTE_6(0x00) |
                      CAN_WORD1_DATA_BYTE_7(0x00);
        /* Initialize the message buffer 1 - Tx */
        /* CAN0_CS1: ??=0,??=0,??=0,??=0,CODE=8,??=0,SRR=0,IDE=0,RTR=0,DLC=0,TIME_STAMP=0 */
        CAN0_CS1 = (CAN_CS_CODE(0x08) | CAN_CS_DLC(0x00) | CAN_CS_TIME_STAMP(0x00));
        /* CAN0_ID1: PRIO=0,STD=0,EXT=0 */
        CAN0_ID1 = (CAN_ID_PRIO(0x00) | CAN_ID_STD(0x00) | CAN_ID_EXT(0x00));
        /* CAN0_WORD01: DATA_BYTE_0=0,DATA_BYTE_1=0,DATA_BYTE_2=0,DATA_BYTE_3=0 */
        CAN0_WORD01 = CAN_WORD0_DATA_BYTE_0(0x00) |
                      CAN_WORD0_DATA_BYTE_1(0x00) |
                      CAN_WORD0_DATA_BYTE_2(0x00) |
                      CAN_WORD0_DATA_BYTE_3(0x00);
        /* CAN0_WORD11: DATA_BYTE_4=0,DATA_BYTE_5=0,DATA_BYTE_6=0,DATA_BYTE_7=0 */
        CAN0_WORD11 = CAN_WORD1_DATA_BYTE_4(0x00) |
                      CAN_WORD1_DATA_BYTE_5(0x00) |
                      CAN_WORD1_DATA_BYTE_6(0x00) |
                      CAN_WORD1_DATA_BYTE_7(0x00);
}

 

Some parts are adapted by the CAN-Driver provided by Processor Experts software.

 

Has anybody ideas? Can someone help me, please?

Maybe Freescale support?

If you need further information, let my know and I will provide!

 

Thank you very much!

 

Manuel

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