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K70 DDR Init Lock up after enabling DDR controller clock in SIM_SCGC3

Question asked by pbanta on Jun 2, 2014
Latest reply on Jun 2, 2014 by pbanta

I have a new revision of our K70 board that I'm trying to bring up.  So far I have no problems running MQX examples from SRAM.  I'm trying to initialize the LPDDR and I'm seeing a problem I've never seen before.

 

I have used the K70 DDR configuration tool from here:

 

http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=K70_120&nodeId=01624698C9DE2DDDB1&fpsp=1&tab=Design_Tools_Tab

 

In the C function generated by the tool the first step is to enable the DDR clock gate. (Line 4 in the code snippet below.)  Enabling the clock causes some problem where my PEMicro loses control of the board and the debug session is terminated.

 

    if ((SIM_SCGC3 & SIM_SCGC3_DDR_MASK) != SIM_SCGC3_DDR_MASK)
    {
        // Enable DDR clock gate
        SIM_SCGC3 |= SIM_SCGC3_DDR_MASK;
    }
    else
    {
        // Check to if the DRAMC is already initialized
        if ((DDR_CR00 & 1) == 1)
            return;
    }

 

Has anyone seen anything like this before?  Any advice?

 

Best regards,

 

Paul

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