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i.MX6 CPU cache.

Question asked by Satoshi Shimoda on May 28, 2014
Latest reply on May 29, 2014 by igorpadykov

Hi community,

 

I have some questions about i.MX6S CPU cache.

Please see the questions as following.

 

[Q1]

Actually, i.MX6S cache is changed from invalid to valid when memory access by USB or Ethernet.

It is not expected behavior, so our partner want to find a solution to avoid this issue.

Then, could you let me know the condition to change the cache invalid -> valid?

 

[Q2]

Could you let me know the condition to accommodate the cache and memory when cache data and memory data is different?

Is there a possibility to satisfy the condition when a peripheral accesses to memory?

 

 

Best Regards,

Satoshi Shimoda

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