AnsweredAssumed Answered

Unable to launch interruput or DMA requests from ADC2 and ADC3 channels

Question asked by David Cantero on May 27, 2014
Latest reply on Oct 22, 2014 by George Pontis

Hello!!

 

I´m implementing an aplication based on application note AN4590 "Using DMA to Emulate ADC Flexible Scan Mode on Kinetis K Series". I was able to integrate ADC drivers and DMA configuration developed in the example above in a MQX 4.0 application, and the adquisition mechanism works fine.

 

I have used the same adc driver API to configure ADC channels 2 and 3 in a software trigger mode (modifiying the ADTRG bit in ADC_SC2 register) and read the results in a periodic interrupt (this interrupt  is in fact launched by ADC channel 1 DMA0 minor loop completion event!!)  The idea was to activate corresponding ADC channel by software trigger and configure a DMA to store results to a buffer automátically using the same mechanism described in the app note AN4590 for DMA channel 0. I have followed the same steps described in the app note for ADC2, ADC3, and DMA configuration with some little modifications described below:

 

1.- Enable ADC2 and ADC 3 in SIM_SCGC6 and SIM_SCGC3 respectively

2.- Enable DMA_MUX1 in SIM_SCGC6

3.- Initialize both ADCs. I have copied the initialization routine for ADC1 changing the registers name to ADC2 and ADC3 correspondingly:

4.- Initailize DMA channel 18 (in channel 2 of the DMA_MUX1) and 19 (in channel 3 of the DMA_MUX1).  I´m not sure if this is correc!!!!!!t

     The DMA lauch an interrupt when finish its major loop. This is used to sinchronize all adquisition mechanism and to store data to a doble buffer before save data to a file.

     The entire mechanism is quite complex due to large number of adquisition channels and different adquisition frequencies:

 

            //****************************************************************************

            //**** DMA channel 2, use for Read ADC result data, form ADC to SRAM *********

            //****************************************************************************

            DMAMUX1_CHCFG2           = DMAMUX_CHCFG_ENBL_MASK|DMAMUX_CHCFG_SOURCE(0x2A);   //DMA source ADC2

            DMA_TCD18_SADDR          = (uint32) &ADC2_RA;                                  //Source address ADC2 result register

            DMA_TCD18_SOFF           = 0x00;                                               //Source address increment, adding "1"

            DMA_TCD18_SLAST          = 0x00;                                               //Source address decrement after major loop complete

            DMA_TCD18_DADDR          = (uint32) &ui_adc2_result[0];                        //Destination address

            DMA_TCD18_DOFF           = 0x02;                                               //Destination address increment, adding "0"

            DMA_TCD18_DLASTSGA       = (uint32) -2*ADC_2_BUFFER_SIZE;                      //Destination address shift, go to back to [0]

            DMA_TCD18_NBYTES_MLNO    = 0x02;                                               //No of bytes minor loop

            DMA_TCD18_BITER_ELINKNO  = (DMA_BITER_ELINKNO_ELINK_MASK|ADC_2_BUFFER_SIZE);   //Major loop step,

            DMA_TCD18_CITER_ELINKNO  = (DMA_CITER_ELINKNO_ELINK_MASK|ADC_2_BUFFER_SIZE);   //Major loop step,

            DMA_TCD18_ATTR           = DMA_ATTR_SSIZE(0)|DMA_ATTR_DSIZE(0);                //Source a destination size, 8bit

            DMA_TCD19_CSR            = /*(DMA_CSR_MAJORLINKCH(0)|DMA_CSR_MAJORELINK_MASK)|*/   //Major loop finished start request for Channel 0

                                                      DMA_CSR_INTMAJOR_MASK | DMA_CSR_INTHALF_MASK;       //Irq. enable, full transfer, half complet transfer

            DMA_ERQ                 |= DMA_ERQ_ERQ18_MASK; 

                                         

 

5.- In the periodic interrupt,  trigger correspnding ADC module and channel (something like this):

 

    switch (ch_select_cnt) {

        case 0:

            ADC2_SC1A = uc_adc2_3_mux[0];

        break;

 

 

 

Unafortunately result buffers remain empty, so DMAs are not been launched. I have configure a ADC conversion complete interrupt in all ADCs (1, 2 and 3)  but only the ADC1 response routine caugth the interruption.

 

 

Wow!!! is a very large explanation!!!!!!  The question is, Do you see something wrong in the steps described above? some idea to solve this issue? Do you had a similar problem once?

 

Thanks in advance!!!!

 

 

 

 

David

Outcomes