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im6q - undesire arm clock root frequency

Question asked by Anson Tiong on May 24, 2014
Latest reply on Jun 3, 2014 by igorpadykov

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SETTING:

PLL_ARM divider set to 16, Clock divider set to 0.

Thus, ARM clock root = 24 / 2 * 16 / ( 0 + 1)

                     = 192 Mhz

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CODE:

while(1){

     counter++;

     if (counter >= 0x40000000){     // if counter >= 1 Giga

          toggleGPIOPIN();

          resetCounter();

     }

}

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FOR 'counter++' part, 3 line assembly code is generated by the compiler:

LOAD

ADD

BRANCH

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Thus at least 3 clock cycle for the 'counter++' loop.

Time between GPIO PIN toggle should be at least  = (3 x 1 Gig) / 192 Meg

                                                 = 15.625 second

 

BUT the problem occur. Time between GPIO toggle is ~5 second (measure by oscilloscope)

Means the arm clock root running at least = 5 / (3 x 1Gig)

                                          = 600 Mhz

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I did try to set arm clock root to 800Mhz, but the result shows it run more then 2GHz.

 

WHAT IS HAPPENING??

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