Kinetis K61 Core clock initialization to 150Mhz

[nareshrana]

we are using following initialization routines (generated using PE) to run the core at 150Mhz. but there is exception thrown at following instruction (marked in bold orange color). Presently we have commented this instruction and the code/execution works fine. Caveat is that 1ms-On and 1ms-off pulse on the port pin is reported as 508Hz (on DSO) instead of expected 500hz. is there any other way we can verify that core is running at accurately 150 Mhz (with below initialization)?

-------------------------------------------------------

void __init_hardware()

{

SCB_VTOR = (UINT32)__vector_table; /* Set the interrupt vector table position */

        /*

Disable the Watchdog because it may reset the core before entering main().

There are 2 unlock words which shall be provided in sequence before

accessing the control register.

*/

WDOG_UNLOCK = KINETIS_WDOG_UNLOCK_SEQ_1;

WDOG_UNLOCK = KINETIS_WDOG_UNLOCK_SEQ_2;

WDOG_STCTRLH = KINETIS_WDOG_DISABLED_CTRL;

//#ifdef JV_Nodef 

/* System clock initialization */

/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=3,OUTDIV4=3,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */

SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |

  SIM_CLKDIV1_OUTDIV2(0x01) |

  SIM_CLKDIV1_OUTDIV3(0x03) |

  SIM_CLKDIV1_OUTDIV4(0x03); /* Set the system prescalers to safe value */

/* SIM_SCGC5: PORTC=1,PORTB=1,PORTA=1 */

SIM_SCGC5 |= SIM_SCGC5_PORTC_MASK |

  SIM_SCGC5_PORTB_MASK |

  SIM_SCGC5_PORTA_MASK;   /* Enable clock gate for ports to enable pin routing */

if ((PMC_REGSC & PMC_REGSC_ACKISO_MASK) != 0x0U) {

/* PMC_REGSC: ACKISO=1 */

PMC_REGSC |= PMC_REGSC_ACKISO_MASK; /* Release IO pads after wakeup from VLLS mode. */

}

/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=5,OUTDIV4=5,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */

SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |

  SIM_CLKDIV1_OUTDIV2(0x01) |

  SIM_CLKDIV1_OUTDIV3(0x05) |

  SIM_CLKDIV1_OUTDIV4(0x05); /* Update system prescalers */

/* SIM_SOPT2: PLLFLLSEL=0 */

SIM_SOPT2 &= (UINT32)~(UINT32)(SIM_SOPT2_PLLFLLSEL(0x03)); /* Select FLL as a clock source for various peripherals */

/* SIM_SOPT1: OSC32KSEL=0 */

SIM_SOPT1 &= (UINT32)~(UINT32)(SIM_SOPT1_OSC32KSEL_MASK); /* System oscillator drives 32 kHz clock for various peripherals */

/* SIM_SCGC1: OSC1=1 */

SIM_SCGC1 |= SIM_SCGC1_OSC1_MASK;

/* PORTA_PCR18: ISF=0,MUX=0 */

PORTA_PCR18 &= (UINT32)~(UINT32)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));

/* Switch to FBE Mode */

/* MCG_C7: OSCSEL=0 */

MCG_C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL_MASK);

/* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=0,LP=0,IRCS=0 */

MCG_C2 = MCG_C2_RANGE0(0x02);

/* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */

OSC0_CR = OSC_CR_ERCLKEN_MASK;

/* OSC1_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */

OSC1_CR = OSC_CR_ERCLKEN_MASK;

/* MCG_C1: CLKS=2,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */

MCG_C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x05) | MCG_C1_IRCLKEN_MASK);

/* MCG_C4: DMX32=0,DRST_DRS=0 */

MCG_C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));

/* MCG_C5: PLLREFSEL0=0,PLLCLKEN0=0,PLLSTEN0=0,??=0,??=0,PRDIV0=3 */

MCG_C5 = MCG_C5_PRDIV0(0x03);

/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=8 */

MCG_C6 = MCG_C6_VDIV0(0x08);

/* MCG_C11: PLLREFSEL1=0,PLLCLKEN1=0,PLLSTEN1=0,PLLCS=0,??=0,PRDIV1=3 */

          //MCG_C11 = MCG_C11_PRDIV1(0x03);

/* MCG_C11: PLLCLKEN1=1 */

MCG_C11 |= MCG_C11_PLLCLKEN1_MASK;   /* Enable the PLL */

/* MCG_C12: LOLIE1=0,??=0,CME2=0,VDIV1=8 */

MCG_C12 = MCG_C12_VDIV1(0x08);

while((MCG_S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */

}

while((MCG_S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */

}

/* Switch to PBE Mode */

/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=8 */

MCG_C6 = (MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0x08));

while((MCG_S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */

}

while((MCG_S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL locked */

}

/* Switch to PEE Mode */

/* MCG_C1: CLKS=0,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */

MCG_C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x05) | MCG_C1_IRCLKEN_MASK);

while((MCG_S & 0x0CU) != 0x0CU) {    /* Wait until output of the PLL is selected */

          }

Thanks,

Naresh

[santiago_lopez]

Hi Naresh,

Can you let us know the complete part number of your K61 and the value of you crystal/oscillator for the PLL?

Saludos

Santiago Lopez

[nareshrana]

Part number: MK61FX512VMJ15  Oscillator Freq: 50Mhz

Above mentioned problem with higlighted instruction is resolved. we have done following change to instruction. and now it builds without any exception.

seems like clock settings if "OR"ed with the existing bit configurations are acceptable but same if assigned (as in the first instruction below) disturbs all the bits and generate exception.

MCG_C11 = MCG_C11_PRDIV1(0x03); <-- instruction with exception

MCG_C11 |= MCG_C11_PRDIV1(0x03); <-- updated instruction without exception

[Wlodek_D_]

Hello,

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