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iMX6 : How to configure the display interface of the IPU (for a lcd panel) synchronised by an input signal (VSYNC from an other panel)

Question asked by Jerome Gendron on May 22, 2014

Hello everyone

I'm using a Nitrogen_6X (iMX6Q) board from Boundary Devices (from SabreLite design reference I think) with a lcd panel (also from Boundary : Nit6X_800x480) connected on the parallel RGB interface (J15 connector of the board ==> DISP0_DAT[0..23] pads of the i.MX6).

The configuration of the panel is : 800x480 RGB parallel 666, pixel clock = 27 MHz, frame rate = 57,544 Hz.

I'm using the latest Linux kernel from boundary github : 3.10.17_1.0.0_ga (boundarydevices/linux-imx6 · GitHub), wich include the support of the board and the panel.

Boot args : ... video=mxcfb0:dev=lcd,CLAA-WVGA,if=RGB666 video=mxcfb1:off video=mxcfb2:off video=mxcfb3:off fbmem=28M ...


I want that the synchronization signals for the display be synchronized from an external VSYNC signal coming from an other panel (with the same specifications : frame rate, ...).

For the validation of this solution, the external VSYNC signal is connected to the CSI1_VSYNC of the IPU2 (pad EIM_DA12, pin 28 of J12 on the Nitrogen_6X board).


After reading (a large number of times...) the chapter 37 (IPU) and particularly the 37.4 (Display Port) of the iMX6 Application Processor Reference, I think that the necessary steps are :

    1) modify the device tree file of the board in order to :

        - map EIM_DA12 on IPU2_CSI1_VSYNC

        - map DISP0_DAT[0..23] and synchronizations signals (DI0_DISP_CLK, DI0_PIN2=HSYNC, DI0_PIN3=VSYNC) to the IPU2, because the external VSYNC is connected to IPU2_CSI1_VSYNC

    2) patch the kernel IPU display driver : modify the configuration of the timing generator used for the generation of the waveforms of the synchronizations pins (DI0_PIN2 and DI0_PIN3)

        the idea is to clear the counters with the external VSYNC (IPU2_CSI1_VSYNC)

First of all is it correct ?


Here are the modifications I made in the kernel files :

    1) arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi, cf tag "JGe" in the corresponding attached file

    2) drivers/mxc/ipu3/ipu_disp.c, function ipu_init_sync_panel(), tag "JGe" in the corresponding attached file



But it doesn't work....

The external VSYNC is generated with a waveform generator with the corrects parameters (pulse duration, frequency, amplitude, ...) but the HSYNC and VSYNC are not generated on the DIO_PINi pins.


Has anybody a suggestion / solution for my problem ?

And is it really doable ?

Thanks a lot !

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