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How is the NVIC wired up?

Question asked by Laartoor on May 21, 2014
Latest reply on May 23, 2014 by Adrian Cano

I wonder how the peripheral interrupt inputs are connected to the Kinetis processors, especially the Kx0 series. According to the ARM documentation, there are two possibilities: as level sensitive, or as pulse sensitive. I could not find anything about this in the Kinetis documentation, so could someone help me out?

 

As the peripherals all have their own interrupt flags, which can be cleared independently from the NVIC, I strongly suspect that Freescale has chosen a level-sensitive implementation. There are subtle differences in behavior between the two with regards to when an interrupt becomes pending, and in order to avoid surprises, it would be very helpful to know which implementation was selected for each peripheral.

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