We are developing a device based on a Congatec QMX6Q CoM. The OS used is Windows Embedded Compact 7 based on the binary version of the BSP made by Adeneo. The device relies on a GPIO pin generating an interrupt and we are having some issues getting this to work properly.
What we are trying to do is configure the GPIO pin as input and configure it to generate an interrupt event on a falling edge. We use the GPIO driver provided in the BSP for this. Configuring the pin for writing and reading works well, but when we initiate the interrupt we get some strange behavoir. After initiating the interrupt, passing along an event handle to our own Interrupt Service Thread, the event is repeatedly signaled without the state of the GPIO pin being changed. The frequency of the false incoming interrupts seems to vary depending on if we use other functions or not (outputting debug messages on a UART increases the frequency a lot). Due to the repeated false interrupts triggering so frequently, I have been unable to verify if changing the GPIO pin state triggers the "wanted" interrupts, but indications are it does not.
While investigating I have extracted the GPIO configuration which shows the values from the i.MX processor GPIO registers, and the interesting find here is that the IMR bit for the pin is cleared. From what I understand this means that the interrupt is disabled and it is consistent with the indications that the "wanted" interrupts are not triggered. But where are the false interrupts coming from? I'm guessing some other driver using interrupts are triggering the GPIO interrupts, but is there any way I can confirm this? What happens when a system interrupt is set to an IRQ on the processor where the IMR bit is not set, could this cause these false interrupts?
Any suggestions on what might be causing this issue or how to track it down will be greatly appreciated.
Congatec CoM used
Adeneo BSP used