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Does the second SDMA channel on the MPC8569E interface the local bus or the second DDR controller?

Question asked by Ignacio Martin on May 13, 2014
Latest reply on May 15, 2014 by Serguei Podiatchev

According to the QUICC Engine Reference Manual (QEIWRM Rev. 4.5) "On the MPC8569E, one channel interfaces with the ECM through the SDMA system bus interface, the other

channel interfaces with the secondary DDR interface." Data paths in Figure 3-4 does also reflect this statement. In contrast, according to the MPC8569E Reference Manual MPC8569ERM Rev. 2, regarding the QUICC Engine interface data paths  it is said: "The data paths include a path from the SDMA system bus interface to targets connected to the ECM and a direct connection from the SDMA secondary bus interface to the local bus controller.". This is correctly reflected Figure 21-2. I've looked through the Errata to MPC8569E Reference Manual but I haven't found anything related.


In view of this conflicting information, which one should I consider correct?