I’m new here. Stuck with confusing/conflicting statements in Freescale’s documentation about VLPR mode, the clock frequency limits in that mode and IRC clock frequency. Currently I am developing with the MK20DX256VLL7, 72 MHz Kinetis K20 device in 100 LQFP package. Freescale’s support for Kinetis links to this community for support, so please help me understand what is going on.
I used these documents:
Please bare with me as I go though the statements that I’ve found:
Kinetis Peripheral Module Quick Reference Guide Rev.2 08/2012:
1) Section 4.1.2, page 44: “…and a fast IRC with a frequency of ~4 MHz (with a fixed divide by 2).”
I’m already confused here. When taking a look at the schematic of the MCG in section 24.1.1 on page 506 of the reference manual there is no fixed divide by 2 on the output of the fast internal reference clock. There is a /2^n with n being 0..7. This divider is set by MCG_SC[FCRDIV] which states a divide factor of 1, or 2^0 being the lowest. This means that the output of this divider is still at 4 MHz if MCG_SC[FCRDIV] is set to ‘0b000’. The description of the FCRDIV bit reinforces that by saying
the resulting frequency will be in the range 31.25 kHz to 4MHz.”
2) Section 18.104.22.168, page 47: “…To be able to move the MCU into the VLPR (or wait) mode, the MCG must be set in a low-power, low-frequency mode with MCGCLKOUT <= 2 MHz, This mode is provided by means of selecting the fast IRC when the MCG is set in BLPI mode.”
Actually this is conflicting as well since the reference manual specifically specifies <= 4MHz (see below)
K20 Sub-Family Reference Manual K20P100M72SF1RM Rev. 1.1, Dec 2012:
3) Section 5.3, diagram on page shows fast IRC being 4 MHz
Well that is clear, the actual clock frequency directly from the fast IRC is 4MHz, regardless what comes directly after.
4) Section 5.4.1, Table 5-1, page 166: “Internal Reference (MCGIRCCLK) | RUN mode: 30-40 kHz or 2MHz | VLPR mode: 4 MHz only “
Why is there a difference between the max frequency of MCGIRCCLK in normal RUN and VLPR mode the latter having a higher clock frequency? That is counter intuitive.
5) Same table, pages 165 and 166: in VLPR mode the clocks for core, system, bus and MCGOUTCLK can be up to 4 MHz
6) Section 7.2, Table 7-1 on page 190 agreed with the above in describing the VLPR mode.
OK so here it states that in VLPR I must select the fast IRC, being 4 MHz for MCGOUTCLK. In addition I can choose any value for the FCRDIV bit since the MCGOUTCLK will be 4MHz at max. In addition the clock dividers for the core/system and bus can be set to ‘divide by 1’ as they are allowed to run at 4MHz maximum. (Flash of course only at 1 MHz).
7) Section 14.4.1, table 14-7, page 304: “transition 3 from RUN to VLPR: reduce system, bus and core frequency to 2 MHz or less”
Huh? I just figured out that it could be 4MHz. So what now?
8) Section 22.214.171.124, table 24-16, page 524, note 1: “If entering VLPR mode, MCG has to be configured and enter BLPE mode or BLPI mode with the 4 MHz IRC clock selected (C2[IRCS]=1).”
That is kind of strange. If I go into BLPE mode but set C2[IRCS] = 1 the C1[CLKS] is still set to the external clock. So MCGOUTCLK is taken from the external clock instead of the fast IRC at 4MHz. Shouldn’t it be that for VLPR mode you must always go into BLPI mode? Then again, can you even go there directly from BLPE? Not according to the MCG mode state diagram in section 24.4.1 on page 520.
So my questions:
- Is there a fixed divide by 2 after the fast IRC (4 MHz)?
- Which maximum frequencies do I need to set in VLPR mode for core/system and bus: 4MHz or 2MHz? I’m not looking for an answer like “go for 2MHz that’s safe”, but the actual reason.
- What about the BLPE mode and VLPR? Is that even possible?
- If using the fast IRC in normal RUN mode, what is the (max) frequency of MCGIRCCLK, 2MHz or 4MHz? And moreover, why?
edit: layout & typo