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[imx6] PLLv3 clock change

Question asked by jiadawang on May 12, 2014
Latest reply on May 11, 2016 by Nori Shinozaki



According to User manual

section PLL clock change

- "Before changing the PLL setting, power it down. Power up the PLL after the change"

But currently neither 3.10 FSL BSP

nor 3.15 mainline kernel

is doing power down/up when changing of PLL clock rate in set_rate() interface.

I do find one patch from Russell King

[134/222] ARM: imx: keep PLLs in bypass while they're locking - Patchwork

in this patch PLL is set to bypass mode before change its rate


my question is:

what is the proper operation to change PLL rate? should pllv3 driver power down/up PLL clock just as user manual stated.

If pllv3 driver keeps current behavior (directly change clock rate with out power down/up or set it to bypass mode),

is there any potential problem, like clock glitch?