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K20DX256VMD10 SPI slave problem /works on a K20DX256ZVMD10

Question asked by Tom Junkans on May 6, 2014
Latest reply on May 7, 2014 by Tom Junkans

I am having problems using the K20DX256VMD10 is SPI slave mode, I get an extra zero bit shifted into the RXFIFO resulting in my 32-bit receive frame being shifted one bit to the right. I send (0xE001 0000) but the K20 reads (0x7000 8000). I am using the exact same SPI software I have running on three other projects using a K20DX256ZVMD10 processor, and they all work fine. I have tried this same exact SPI driver software with K40, K60 & K70 tower boards and they all work fine. The only thing I did different is use SPI2 on port-D, where the other projects I use SPI2 on port-B.

Here is what my 32-bit frame looks like:Yellow is SPI-In, green is clock, red=Out, blue=CSscope_881.bmp


Here is a close-up of the 1st 16-bits:scope_882.bmp

I am changing on leading edge and capturing on trailing edge. My SPI2_POPR is all zeros at the start, but the K20 sees 0x7000 in the 1st 16-bits, it should see 0xE001, like the scope shows. The 2nd 16-bits reads 0x8000, and the scope clearly shows all zeros.


This is crazy! everything looks good. I plug any of my other three K20DX256ZVMD10 project boards onto this SPI master and they all read (0xE001 0000) just like they should.


Here is my SPI setup code for both projects, the project that works uses SPI2 on port-B, the broke project uses SPI2 on port-D, that is the only difference except the processors are a different flavor (good is MK20DX256ZVMD10, the bad is MK20DX256VMD10)

int_32 spiConfigSpi2Slave()


      SIM_SCGC3 |= (1UL <<  SIM_SCGC3_SPI2_SHIFT);     // Enable SPI2      

      SIM_SCGC5 |= (1UL << SIM_SCGC5_PORTD_SHIFT);     // Enable Clock to Port D for new Qlx cards.

      SIM_SCGC5 |= (1UL << SIM_SCGC5_PORTB_SHIFT);     // Enable Clock to Port D for new Qlx cards.

      SPI2_SR |= SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK ; // Clear the SPI2 slave interrupt

      SPI2_RSER = (1UL << SPI_RSER_RFDF_RE_SHIFT);     // SPI2 interrupt when SPI2 RX FIFO is not empty

      SPI2_CTAR0_SLAVE = TJ32BIT_SPI_SLAVE;  // TJdriver-32 bits slave SPI, clk idle high, trailing edge capture.                      


        | (1UL << SPI_MCR_MTFE_SHIFT)

        | (1UL << SPI_MCR_CLR_RXF_SHIFT)

        | (1UL << SPI_MCR_PCSIS_SHIFT) );  // Continuous, modified timing, run SPI


#if REAL_SCALE_CARD     // for the real new scale card

      // Setup processor pins for SPI.

      PORTD_PCR11 = (1UL << 9);          //SPI alt2, CS0

      PORTD_PCR12 = (1UL << 9);          //SPI alt2, Clock

      PORTD_PCR13 = ((1UL << 9) | (1UL << 6)); //SPI alt2, Out set to hi-drive power

      PORTD_PCR14 = (1UL << 9);          //SPI alt2, In


      PORTB_PCR20 = (1UL << 9);          //SPI alt2, CS0

      PORTB_PCR21 = (1UL << 9);          //SPI alt2, Clock

      PORTB_PCR22 = ((1UL << 9) | (1UL << 6)); //SPI alt2, Out set to hi-drive power

      PORTB_PCR23 = (1UL << 9);          //SPI alt2, In


      SPI2_MCR  |= (1UL <<  SPI_MCR_CLR_RXF_SHIFT);    // clear RXFIFO counter




If anyone has an idea of what my problem is I would appreciate some help. Thanks in advance.