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K70 LCDC configuration for VGA display

Question asked by Oliver Gonzalez on May 6, 2014
Latest reply on Aug 25, 2014 by Melissa A Hunter

Hello. I've been trying (for almost 2 months) to set the LCDC module of the TWR K70 board with no succes. I need to display a number in a plain VGA PC monitor connecting the VGA DB-15. connector in a board.

I am trying first to get the signals out of the k70 but nothing... I don't even see the Hsync or Vsync signals.


This is my program, it is just configuration to turn on the LCDC but nothing, what is wrong? Programm is full of comments since I am learning and reading the data sheet and getting the elements I need to complete the project I am working for, so I am sorry because it is quite messy but Looks like I am very near of the goal.


Here is my set up, the board, getting out the H & V signals to the oscilloscope of the elevator connector but nothing.



2014-05-06 11-04-15.456.jpg



#include "derivative.h" /* include peripheral declarations */



#define XMAX  800

#define YMAX  600

#define ALT7  0x00000700


int arreglo [4000]={0xaaaaaaaa};

int *ptr;



int main(void)



        int counter = 0;


        ptr = (void *)&arreglo;


        SIM_SCGC5 = (1<<14) | (1<<9);    //activate PORTA and PORTF


        PORTA_PCR10 = 0x00000120;    //config LEDs of twr K70

        PORTA_PCR11 = 0x00000120;

        PORTA_PCR28 = 0x00000120;

        PORTA_PCR29 = 0x00000120;


        //GPIO pag 2147

        GPIOA_PDOR = 0x30000C00;    //field descriptions

        GPIOA_PDDR = 0x30000C00;




    //    PORTF_PCR2 = 0x00000120;

    //    PORTF_PCR3 = 0x00000120;

        GPIOF_PDOR = 0x0000000C;    //field descriptions

        GPIOF_PDDR = 0x0000000C;


        //señal de horizontal GLCD_HFS que es PTF2  que es pin N16 está en D27 de J7B  LCD_HSYNC

        //señal de vertical   GLCD_VFS que es PTF3  que es pin M16 está en D28 de J7B  LCD_VSYNC


        //señal de horizontal GLCD_HFS que es PTD14 que es pin E5 está en D27 de J7B  LCD_HSYNC

        //señal de vertical   GLCD_VFS que es PTD15 que es pin E4 está en D28 de J7B  LCD_VSYNC


        //GPIOF_PDOR = 0x0000000C;

        //GPIOF_PSOR =

        //GPIOF_PCOR =

        //GPIOF_PTOR =

        //GPIOF_PDIR =

        //GPIOF_PDDR = 0x0000000C;



        //lo referente al LCDC pag 193






        //CLOCK DISTRIBUTION pag 229      

        //diagrama del clock en pag 214 y 636

        MCG_C5 = 0b11000000;        //seleccionamos 0SC1 como fuente de clock bit 7 (0 osc1 de 12Mhz y 1 osc0 de 50Mhz)

                                    //y habilitamos MCGPLL0CLK  MCG Control 5 Register pag 643


        MCG_C6 = 0b00000000;        //MCG Control 6 Register (MCG_C6) pag 644


        //MCG_C11 = 0b //MCG Control 11 Register

        //pag 214 Bus clock, MCGPLL0CLK, MCGPLL1CLK, OSC0ERCLK son fuentes de clock del LCDC

        //detalles de clock , 221, 217,


        SIM_SOPT2 = 1<<26 | 0<<14; //selecciona la fuente de clock  

        //[LCDC_LCDCSRC] bits 27 y 26,  0 Bus clock, 1 MCGPLL0CLK, 2 MCGPLL1CLK, 3 OSC0ERCLK

        //[LCDC_CLKSEL] bit 14 pag 324 0 Clock divider LCDC pixel clock, 1 EXTAL1 clock.


        SIM_CLKDIV3 = 1<<16 | 1<<8;  // pag355

        //LCDC Clock divider fraction bits 16 al 27

        //This field sets the fraction multiply value for the fractional clock divider used as a source for LCDC pixel

        //clock. The source clock for the fractional clock divider is set by the SOPT2 LCDCSRC[1:0] register bit.

        //Divider output clock = Divider input clock*((LCDCFRAC+1)/(LCDCDIV+1))

        //LCDCFRAC bits 8 al 15


        SIM_SCGC3 =  1<<22;         //pag 338 LCDC clock gate control, 1 Clock is enabled.








        //Chip configuration pag 81

        //The Memory Protection Unit must be configured to allow the LCDC to access the DRAM.


        //pines del micro y nombres pag 297


        //crossbar switch pag 100

        //Master module LCDC graphic window  Master port number  5

        //Master module LCDC background plane  Master port number  4






        //LCDC explicación de cómo funciona el LCDC pag 2215



         //signals Multiplexing module pag 273


            PORTF_PCR2 = 0x00000700;    //alt7 GLCD_HFS pag 280

            PORTF_PCR3 = 0x00000700;    //alt7 GLCD_VFS pag 280


            //PORTF_PCR0 = ALT7; // Graphic LCD PCLK, Schematic PTF0

            //PORTF_PCR1 = ALT7; // Graphic LCD DE, Schematic PTF1

            //PORTF_PCR2 = ALT7; // Graphic LCD HSYNC, Schematic PTF2

            //PORTF_PCR3 = ALT7; // Graphic LCD VSYNC, Schematic PTF3


            PORTF_PCR4 = ALT7; // Graphic LCD D[0], Schematic PTF4

            PORTF_PCR5 = ALT7; // Graphic LCD D[1], Schematic PTF5

            PORTF_PCR6 = ALT7; // Graphic LCD D[2], Schematic PTF6

            PORTF_PCR7 = ALT7; // Graphic LCD D[3], Schematic PTF7



        //configuración de gráficos:  LCDC (Liquid Cristal Display Controller) Pag 2183

        //LCDC_LSSAR = (void *)&ptr;        //LCDC screen start address register

        LCDC_LSSAR = ((int)ptr)<<1;        //LCDC screen start address register

        LCDC_LSR = XMAX<<20 | YMAX;    //LCDC size register  XMAX y YMAX ** Aguas con XMAX si es o no dividido por 16

        LCDC_LVPWR = XMAX;                //LCDC virtual page width register representa la dirección de inicio de una línea desplegada

        LCDC_LCPR =    0;                //LCDC cursor position register tipo de cursor, e inicio en X,Y del cursor

        LCDC_LCWHB = 0;                //LCDC cursor width, height, and blink register

        LCDC_LCCMR = 0;                //LCDC color cursor mapping register

        //pag 2194 - LCDC_LPCR

         //LCDC_LPCR = 0b 1100 0100 1100 1010 1000 0000 1000 0001; //configura algo de tiempos LCDC panel configuration register    2194 his register defines all properties of the LCD screen.

        LCDC_LPCR = 0b11000100110010101000000010000001;

        LCDC_LHCR = 10<<26|10<<8|50;    //LCDC horizontal configuration register

        LCDC_LVCR = 15<<26|15<<8|15;    //LCDC vertical configuration register

        LCDC_LPOR = 0;                //LCDC panning offset register

        LCDC_LPCCR = 1<<7;            //LCDC PWM contrast control register

        LCDC_LDCR = 1<<31;            //LCDC DMA control register

        LCDC_LRMCR = 1;             //LCDC refresh mode control register 0 Disable self-refresh

        LCDC_LICR = 0;                //LCDC interrupt configuration register

                //If an EOF interrupt is desired, then set INTCON=0 and LIER[EOF_EN]=1.

                //If a BOF interrupt is desired, then set INTCON=1 and LIER[BOF_EN]=1.

        LCDC_LIER = 0;                //LCDC interrupt enable register

        LCDC_LISR = 0;                //LCDC interrupt status register

        LCDC_LGWSAR = 0;            //LCDC graphic window start address register  2207

        LCDC_LGWSR = 800<<20 | 600;    //LCDC graphic window size register

        LCDC_LGWVPWR = 4;            //LCDC graphic window virtual page width register

        LCDC_LGWPOR = 1;            //LCDC graphic window panning offset register

        LCDC_LGWPR = 0;                //LCDC graphic window position register

        LCDC_LGWCR = 0x0f<<24|1<<23|1<<22|4<<12|4<<6|4;            //LCDC graphic window control register

        LCDC_LGWDCR = 1<<31;         //LCDC graphic window DMA control register

        LCDC_LAUSCR = 0;            //LCDC AUS mode control register

        LCDC_LAUSCCR = 0;            //LCDC AUS mode cursor control register


        SIM_MCR = 1<<16;            //LCDSTART bit 16 // pag 357      




            for(counter=500000; counter > 0; counter--)



               GPIOA_PTOR = 0x30000C00;             

          //     GPIOF_PTOR = 0x0000000C;



    return 0;