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DDR3 clock domain

Question asked by alessandro piscozzo on May 6, 2014
Latest reply on May 6, 2014 by igorpadykov


I've been working on the hardware of a board with a 4core i.MX6.


I have 4 memory chip, all DDR3.


From the reference design (MCIMX6Q-SMART DEVICE BOARD, pag. 4), I see that:

- two DDR3 modules are connected to DRAM_SDCLK0

- two DDR3 modules are connected to DRAM_SDCLK1


The clock enable used is DRAM_SDCKE0 while DRAM_SDCKE1 is unconnected.

Also DRAM_SDODT0 controls the on-die termination of all the four modules while DRAM_SDODT1 is unconnected.


Can anyone explain why?


Thank you in advance,