AnsweredAssumed Answered

MPC5606S PWM output

Question asked by Miquel Soler Mir on May 5, 2014
Latest reply on May 13, 2014 by Miquel Soler Mir

Hi, I'm new in Qoriwa architecture.

 

I'm using the MPC5606S-Demo board.

 

I have a problem in the TFT blacklight regulation.

 

I'm trying to output a PWM signal from PG12 output line. The output is every time low.

 

I try to output the PWM in likes PJ14 and PK0 and are working fine but when I try in lines PG12 / PK10 and PK11 doesn't  work.

 

I'm using the code warrions IDE and the code is on bottom of the post:

 

I don't know what I'm doing wrong ?

 

Can some body help me in this problem.

 

Thanks in advance.

 

 

 

 

 

void initEMIOS_0(void)

  ME.PCTL[72].R = 0x01;       // MPC56xxB/P/S EMIOS 0:  select ME.RUNPC[0]

  CGM.AC1_SC.R = 0x03000000;  // MPC56xxS: Select aux. set 1 clock to be FMPLL0

  CGM.AC1_DC.B.DE0    = 1;       // MPC56xxS: Enable aux. clock to eMIOS0

  EMIOS_0.MCR.B.GPRE  = 63;   // Divide 64 MHz sysclk by 63+1 = 64 for 1MHz eMIOS clk

  EMIOS_0.MCR.B.GPREN = 1;      // Enable eMIOS clock

  EMIOS_0.MCR.B.GTBE  = 1;    // Enable global time base

  EMIOS_0.MCR.B.FRZ   = 1;    // Enable stopping channels when in debug mode

}

 

void initEMIOS_0ch23(void)            // EMIOS 0 CH 23: Modulus Up Counter

{       

  EMIOS_0.CH[23].CADR.R       = 999;  // Period will be 999+1 = 1000 clocks (1 msec)

  EMIOS_0.CH[23].CCR.B.MODE   = 0x50; // Modulus Counter Buffered (MCB)

  EMIOS_0.CH[23].CCR.B.BSL    = 0x3;    // Use internal counter

  EMIOS_0.CH[23].CCR.B.UCPRE  = 0;      // Set channel prescaler to divide by 1

  EMIOS_0.CH[23].CCR.B.UCPEN  = 1;    // Enable prescaler counter to count

  EMIOS_0.CH[23].CCR.B.FREN   = 1;       // Freeze channel counting when in debug mode

}

 

void initEMIOS_0ch20(void)            // EMIOS 0 CH 20: Output Pulse Width Modulation

{       

  EMIOS_0.CH[20].CADR.R       = 250;  // Leading edge when channel counter bus=500

  EMIOS_0.CH[20].CBDR.R       = 500;  // Trailing edge when channel's counter bus=999

  EMIOS_0.CH[20].CCR.B.BSL    = 0x0;    // Use counter bus A (default)

  EMIOS_0.CH[20].CCR.B.EDPOL  = 1;      // Polarity-leading edge sets pin; trailing clears

  EMIOS_0.CH[20].CCR.B.MODE   = 0x60; // Mode is OPWM Buffered

  SIU.PCR[PJ14].R           = 0x0800; // Set PG12 as output with opt3

}

 

void initEMIOS_0ch18(void)            // EMIOS 0 CH 18: Output Pulse Width Modulation

{       

  EMIOS_0.CH[18].CADR.R       = 250;  // Leading edge when channel counter bus=500

  EMIOS_0.CH[18].CBDR.R       = 750;  // Trailing edge when channel's counter bus=999

  EMIOS_0.CH[18].CCR.B.BSL    = 0x0;    // Use counter bus A (default)

  EMIOS_0.CH[18].CCR.B.EDPOL  = 1;      // Polarity-leading edge sets pin; trailing clears

  EMIOS_0.CH[18].CCR.B.MODE   = 0x60; // Mode is OPWM Buffered

  SIU.PCR[PK0].R            = 0x0800; // Set PG12 as output with opt3

}

 

void initEMIOS_0ch15(void)            // EMIOS 0 CH 18: Output Pulse Width Modulation

{       

  EMIOS_0.CH[15].CADR.R       = 250;  // Leading edge when channel counter bus=500

  EMIOS_0.CH[15].CBDR.R       = 750;  // Trailing edge when channel's counter bus=999

  EMIOS_0.CH[15].CCR.B.BSL    = 0x0;    // Use counter bus A (default)

  EMIOS_0.CH[15].CCR.B.EDPOL  = 1;      // Polarity-leading edge sets pin; trailing clears

  EMIOS_0.CH[15].CCR.B.MODE   = 0x60; // Mode is OPWM Buffered

  SIU.PCR[PK10].R            = 0x0800; // Set PG12 as output with opt3

}

 

void initEMIOS_0ch8(void)            // EMIOS 0 CH 8: Output Pulse Width Modulation

{       

  EMIOS_0.CH[8].CADR.R       = 250;  // Leading edge when channel counter bus=500

  EMIOS_0.CH[8].CBDR.R       = 750;  // Trailing edge when channel's counter bus=999

  EMIOS_0.CH[8].CCR.B.BSL    = 0x0;     // Use counter bus A (default)

  EMIOS_0.CH[8].CCR.B.EDPOL  = 1;       // Polarity-leading edge sets pin; trailing clears

  EMIOS_0.CH[8].CCR.B.MODE   = 0x60; // Mode is OPWM Buffered

  SIU.PCR[PG12].R          = 0x0C00; // Set PG12 as output with opt3

}

 

And in Main:

  initEMIOS_0();

  initEMIOS_0ch23();     

  initEMIOS_0ch20();

  initEMIOS_0ch18();

  initEMIOS_0ch15();

  initEMIOS_0ch8();

Outcomes