We are using iMX6DL with LPDDR2 (2-channel x32) configuration. We are using micron part MT42L256M64D4LM-25 WT (4 die, each die is 4Gb, each channel is 8Gb). We followed attached reference design shared in SR# 1-1271525975.
We have configured MMDC using the register values from attached xls sheet except we modified the chip select end address (MMDC_MDASP) to indicate each channel size as 1GB.
1) We observed that if code (e.g iMX6 Platform SDK) is loaded to 0x80000000 and executed then one can see the serial output but on exection of IPU display test it fails with undefined instruction. However the same code runs without any issue if its loaded to 0x10000000.
2) Similar observation was seen when code was loaded at 0x80000000 and we were performing random value test on 0x10000000 memory region. The code fails with undefined instruction when memory was written btw 0x40000000 to 0x40100000. At this point, it was noted that some sections of code in 0x80000000 region was corrupted. We are not sure whats the reason as the memory test was confined only to 0x10000000 region and within 1GB range.
1) Should BOOTCFG3[5:4] be configured to 01 to indicate the memory map for LPDDR2 (0x80000000, 0x10000000)? What will be the behavior if MMDC is configured as per the attached xls sheet with BOOTCFG3[5:4] as 00.
2) What is the excepted behavior if we access address beyond the chip select end address? We found that its still possible to read or write to such addresses however not sure if any roll over is happening and to which valid address.
3) If someone has got 2 channel LPDDR2 working, can you pls share the register settings.