Pato Three

Some results with QSPI XIP on the TWR-VF65GS10

Discussion created by Pato Three on Apr 29, 2014
Latest reply on Apr 29, 2014 by Naoum Gitnik

Running on bare-metal a calculation of 50-digits PI after invoquing MQX _icache_disable() and _dcache_disable(), here's what I got:

gcc                            thumb debug      thumb release

qspi clock default      13799010                9803617

qspi clock tweaked     4581872               3280662

(values in microseconds)

 

settings for QSPI clock tweaked:

  ANADIG->PLL2_CTRL = 0x00002001;
  ANADIG->PLL2_PFD = ANADIG_PLL2_PFD_PFD4_FRAC(12);

 

  // QSPI0_CLK_SEL
  CCM->CSCMR1 = (CCM->CSCMR1 & ~CCM_CSCMR1_QSPI0_CLK_SEL_MASK) |
                 0x00000000 * 0 | // PLL3 MAIN CLOCK
                 0x00400000 * 0 | // PLL3 PFD4
                 0x00800000 * 1 | // PLL2 PFD4
                 0x00C00000 * 0;  // PLL1 PFD4

 

  // set QSPI0_EN - Serial CLK
  CCM->CSCDR3 = (CCM->CSCDR3 & ~0x1F) |
                 CCM_CSCDR3_QSPI0_EN_MASK |
                 CCM_CSCDR3_QSPI0_DIV_MASK * 1 |    // X1 clock  /2 divider enable
                 CCM_CSCDR3_QSPI0_X2_DIV_MASK * 1 | // X2 clock  /2 divider enable
                 (1);                             // X4 clock divider 1..4 (1-> /2)

 

  QuadSPI0->SMPR = 0x50000; // DDRSMP 4/5/6 = ok -> using 5

 

CA5 = 500MHz
Platform Bus = 167MHz
IPG = 83.5MHz

 

PLL2 = 528MHz
DIV_SELECT = 1
PFD4_FRAC = 12

QSPI1_DIV = 1 (divide by 2)
QSPI1_X2_DIV = 1 (divide by 2)
QSPI1_X4_DIV[1:0] = 1 (divide by 2)

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