I seem to be running in to the same problem as many people here, struggling to debug a Freescale (8313) processor in a JTAG daisy chain with another device (Spartan 6 FPGA). I am attempting to use the non eclipse based IDE CW V8.8 and a USB TAP. Error generated is "Target processor not recognised"
Reading the documentation*, I am guessing this should be correct for the JTAG initialization file.
generic (1 6) (2 1) (3 0x0000003F)
E300 (1 1) (2 0x65040000) (3 0xA0602400)
The chain looks like this:
TDI -> MPC8313 -> FPGA -> TDO
Ie the Xilinx Spartan 6 is the last device in the chain:
*Documentation for CW V8.8 seems to be patchy on this subject, "CodeWarrior Development Studio for Power Architecture Processors Targeting Manual, Rev. 10.3.3" Section "Using JTAG Configuration File to Specify Multiple Linked Devices on a JTAG Chain" is where I have guessed the generic line from.
The Spartan 6 has an instruction register length of 6, 1 bit bypass register and the bypass instruction is “111111 in binary” or 0x3F.
I am pretty sure my problem is only with the CW config since I am able to perform the following:
1) I can program the FPGA using JTAG using Xilinx Tools with
the complete chain intact.
2) I can debug the 8313 if I remove the FPGA from the chain. (And remove the generic line from the file)
3) JTAG voltages and edges all look good in both configurations.
Does CW V8.8 Support Chains?
Any ideas / Experience?