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DDR3 CR154 Setting

Question asked by Tomoki Okuno on Apr 29, 2014
Latest reply on May 8, 2014 by Tomoki Okuno

Dear Forum members,

 

I would like to know about DDRMC_CR154 Register.

 

A discussions here about DDRMC_CR154 Register exists as follows;

  • Bring up DDR3 Memory on Vybrid (No.383998)
  • DDR3 Intermittent Problem (No.372438)

 

In those discussion, Forum members recommend DDRMC_CR154 change from 0x68200000

to 0x682C0000.In other words DDR_SEL_PAD_Control bit change to DDR3 mode.

 

We use DDR3 SDRAM on Vybrid VF6 Board.

 

What electrical characteristic chenges when we change Bit19-18(DDR_SEL_PAD_Control) in CR154?

 

I hope your reply, for example

  • DQ wave pattern changes.
  • This affects both cold boot and warm boot.
  • After RESET# is de-asserted, Timing of CKE becomes active is chenged.
  • etc...

 

In Reference BSP, DDR_SEL_PAD_Control was set in 00b.

What problem occurs when we use this setting in Si 1.1?

 

I would like you to tell me more about that in detail.

 

Regards,

Tomoki

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