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For the Power-up sequence of MX6DL SABRE-SDP.

Question asked by yuuki on Apr 27, 2014
Latest reply on Apr 29, 2014 by Yuri Muhin

In the SABRE-SDP, MMPF0100F0 and i.MX6DL are used.

 

The output of SW1AB of MMPF0100F0 is connected to VDDARM of i.MX6DL.
And the output of SW1C of MMPF0100F0 is connected to VDDSCC of i.MX6DL.

 

According to description of 6.1.1Device Start-up Configuration ("F0") in MMPF0100 datasheet(Rev7),
- SW1C is outputted after a SW1AB output.
- This interval is 2.0 ms.

 

However, the following is explained by the datasheet of MCIMX6.
"— VDD_ARM_IN and VDD_SOC_IN may be supplied from the same source, or
  — VDD_SOC_IN can be supplied before VDD_ARM_IN with a maximum delay of 1 ms."

 

I think the Power-up sequence of MMPF0100F0 does not match i.MX6.

Does it have any problems?
Does it have any bad effects on i.MX6?

 

Best Regards,

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