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9S12XDP512 PLL set up

Question asked by Robert Hiebert on Apr 19, 2014
Latest reply on May 14, 2014 by Robert Hiebert

I'm having difficulty setting up the PLL. The lock bit doesn't apper to be getting set and I dont know what I'm doing wrong.

 

Here's my code.

 

;***********************************************************************
;
; - Set the Phase Lock Loop for 80MHz and enable the PLL.
;   Crystal frequency is 16MHz
;   PLL frequency is (2*(crystal frequency/(REFDV+1))*(SYNR+1))
;
;***********************************************************************


            bclr  CLKSEL,CLKSEL_PLLSEL ; Clear "PLL Select" bit of
                                       ;"CLKSEL" to derive system
                                       ; clocks from "OSCCLK"
            bclr  PLLCTL,PLLCTL_PLLON  ; Clear "Phase Lock Loop On" bit
                                       ; of "PLLCTL" to turn PLL off
            movb  #$03,REFDV           ; Load "REFDV" with 3d
                                       ;(16MHz/(3+1)=4MHz Bus freq.)
            movb  #$09,SYNR            ; Load "SYNR" with 9d
                                       ;( 4MHz*(9+1)=40MHz Bus freq.)
            bset  PLLCTL,PLLCTL_AUTO   ; Set "Automatic Bandwidth
                                       ; Control bit" of "PLLCTL"
           
            bset  PLLCTL,PLLCTL_PLLON  ; Set "Phase Lock Loop On" bit
                                       ; of "PLLCTL" to turn PLL on at
                                       ; 80MHz)

;***********************************************************************
;
; - Switch to using PLL for clock (40MHz Bus frequency)
;   Bus frequency is half PLL frequency:
;   ((crystal frequency/(RFDV+1))*(SYNR+1))
;
;***********************************************************************

            nop                          ; Wait 1 bus clock cycle
            nop                          ; Wait 1 bus clock cycle
            nop                          ; Wait 1 bus clock cycle
            nop                          ; Wait 1 bus clock cycle
            brclr CRGFLG,CRGFLG_LOCK,*+0 ; Loop until "Lock Status" bit
                                         ; of "CRFLG" is cleared
            bset  CLKSEL,CLKSEL_PLLSEL   ; Set "PLL Select bit" to 
                                         ; derive system clocks from
                                         ; "PLLCLK"
                                        
;======================================================================
;--------------------------- DEBUG INDICATOR --------------------------                                        
;======================================================================                                        
            LDAA  #$80   ; Load accumulator with %1000000
            STAA  PORTA  ; Copy to PORTA (Fuel Pump LED on)
;=====================================================================

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