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How to configure SSI to give the MCLK, BCLK  and LRCLK to external ADC

Question asked by ajithpv on Apr 18, 2014
Latest reply on Apr 21, 2014 by ajithpv

Hi all,

As part of our task, we are using the CS5343 Audio A/D Converter for Audio Input mic setup.

The CS5343 (a simple ADC without any register settings) is not using any external clock source and the 12.288 MHz (256xLRCLK) MCLK has to be given through the SSI sys_clk.

The CS5343 signals are connected to i.MX6DL' AUDMUX port 4 (AUDMUX_AUD4), which in-turn connects to the SSI in the i.MX6DL processor.

I have set the AUDMUX and SSI registers and now I'm getting the MCLK, BCLK and LRCLK when  I probed the signals. But no data is generating from the CS5343 chip.

 

The issue is that, I'm not getting the MCLK as desired while probing and is equal to the BCLK!

 

 

I'm setting SSI's sys clock as 12.28 MHz and I'm expecting the same value on AUDMUX_AUD4_RXC which is connected to the MCLK signal of the ADC.

The BCLK (3.02 MHz) and LRCLK (48 KHz) are coming proper while probing the signal lines, but the MCLK is coming 3.02 MHz instead of 12.28MHz in the AUDMUX_AUD4_RXC line!

More over, in my driver, the MCLK is coming properly (12.28 MHz ) and I'm setting the proper divisions too (that's why the BCLK and LRCLK is coming properly).

 

I have gone through the i.MX6DL reference manual and understand the below details from 61.8.4.1 SSI Clock and Frame Sync Generation,

1) If I have to get the SSI’s sys clock as external output, then I need to drive it through the SRCK port.

2) Right now, I’m getting the MCLK as equivalent as BCLK so hence, I’m suspecting the STCK is driving instead of SRCK line (STCK is equivalent to BLCK from the diagram).

3) I have gone through the Table 61-2. Clock Pin Configurations also but, I didn’t get the actual settings.

 

I would like to share my configuration as below.

1) SSI and AUDMUX settings in the board file as follows:

    static struct mxc_audio_platform_data mx6_iwg15m_mxm_audio_data = {
        .ssi_num = 1, /* SSI number = 2 */
        .src_port = 2, /* Source Port = 2 */
        .ext_port = 4, /* External Port = 4 = AUD4*/

        ...
     };
2) AUDMUX settings in my machine driver as follows:

 

a)    imx_audmux_config(plat->ext_port, plat->src_port); /* clock directions are from i.MX6 SSI to CS5343 since the CS5343 is slave. Data is input to the processor since its Audio-In mic ADC */

 

b)    static int imx_audmux_config(int slave, int master)
       {
        unsigned int ptcr, pdcr;
        slave = slave - 1;
        master = master - 1;

        ptcr = MXC_AUDMUX_V2_PTCR_SYN |
                MXC_AUDMUX_V2_PTCR_TFSDIR |
                MXC_AUDMUX_V2_PTCR_TFSEL(master) |
                MXC_AUDMUX_V2_PTCR_TCLKDIR |
                MXC_AUDMUX_V2_PTCR_TCSEL(master)|
                MXC_AUDMUX_V2_PTCR_RCLKDIR |            /* Newly added for RXC configuration */
                MXC_AUDMUX_V2_PTCR_RCSEL(master);    /* Newly added for RXC port selection */
        pdcr = MXC_AUDMUX_V2_PDCR_RXDSEL(master);
        mxc_audmux_v2_configure_port(slave, ptcr, pdcr);

 

        ptcr = MXC_AUDMUX_V2_PTCR_SYN;
        pdcr = MXC_AUDMUX_V2_PDCR_RXDSEL(slave);
        mxc_audmux_v2_configure_port(master, ptcr, pdcr);

 

        return 0;
}

3) From the AUDMUX_PTCR4 configuration settings:

 

RCLKDIR=1 RXC is an output.

RCSEL[3:0] = 1000 Selects RXC from port2.

 

so, I changed the default configuration from

 

#define MXC_AUDMUX_V2_PTCR_RCSEL(x)   (((x) & 0xf) << 12)        to

#define MXC_AUDMUX_V2_PTCR_RCSEL(x)   (((x) & 0xf) << 15)

 

in the arch/arm/plat-mxc/include/mach/audmux.h file.

 

Still I'm getting the STCK value instead of  SRCK !

I'm also make sure that, the TXDIR and SYS_CLK_EN are enable which is required to drive the SRCK as SSI sys clk.

 

What might be wrong here? Am I missing some other settings which required?

I hereby request you to provide me the settings/configuration/idea for driving the SSI’s sys clock through SRCK port, so that I will get the same SSI’s sys clock in the AUDMUX_AUD4_RXC line.

 

Thanks in advance

Ajith P V

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