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imx6d lpddr2 MT42L256M64D4LM-25 and CS0_END

Question asked by anrov on Apr 16, 2014
Latest reply on Apr 22, 2014 by Yuri Muhin

Our custom board uses this config:

cpu: i.MX6D

lpddr2: MT42L256M64D4LM-25 (2GBytes)

ddr memory map: trying 4KB interleaving




Q1: Why does the "i.Mx6DQSDL LPDDR2 Script Aid" (V0.04) produce these values for CS0_END?

Chan0 CS0_END: 0x00000053  (= 0xa8000000 bytes = 2688MB)

Chan1 CS0_END: 0x00000013  (= 0x28000000 bytes = 640MB)

Q1a: Does this imply that the address space for the ram has a gap between the first 640MB (at channel 1) and the remaining 1408MB (at channel 0)?

Q1b: Given our configuration, what is the base address of our ram: 0x10000000 or 0x80000000?



Q2: What is the purpose of the ddr memory map option "4KB interleaving"? Is there an advantage/disadvantage compared to the fixed 2x32 map?




This is what I have entered into the "Register Configuration" tab in the "i.Mx6DQSDL LPDDR2 Script Aid" (V0.04):