I have a question about i.MX6SDL PLL2 spread spectrum.
A end user is trying to apply the spread spectrum to LCD clock.
We think spread spectrum is applied to PLL2 PFD clock when PLL2 spread spectrum is valid.
And now, the spread spectrum works well on DDR clock line, but does not work well on LCD clock line (IPU1_DI0_CLK) even though LCD clock is provided from PLL2 PFD.
Please see the detail as below.
1. osc_clk(24MHz) --> pll2_528_bus_main_clk(528MHz) --> pll2_pfd_400MHz(396MHz) --> ipu1_di0_clk (132MHz)
2. ocs_clk(24MHz) --> pll2_528_bus_main_clk(528MHz) --> pll2_pfd_400MHz(396MHz) --> periph_clk(396MHz) --> mmdc_ch0_axi_clk(396MHz) --> ipu1_di0_clk(132MHz)
[Clock route setting file]
Function: clk_set_parent() in mx6_clocks_init() function.
DDR clock : ddr_clk.jpg ==> spectrum spread works well.
LCD clock : lcd_clk_2.jpt ==> spectrum spread does not work well. (sorry for hard to see)
Is some additional setting required to apply spread spectrum to IPU1_DI0_CLK?
And if there is a wrong in our understanding, please tell me it.