AnsweredAssumed Answered

Processor Expert Version 10.4 and ADC measurements not working as expected.

Question asked by Kevin McKeever on Apr 15, 2014
Latest reply on Feb 15, 2017 by grant cazinha

I am using the current PE10.4 with the MK10DN512VLL10 processor.  I am setting 5 channels up as single ended inputs. The issue is that two channels read correctly and three channel read either full scale or zero.

The issue that I am seeing with PE10.4 is that the bit ADC_CFG2_MUXSEL_MASK in the ADCx_CFG2 register appears to only get set during initialization method.  As you can see it is set several times during this initialization.  It is not an arrayed byte so this doesn't make much since.  In writing the code this way forces the hardware to either connect all of the ADC channels to "a" or "b" inputs.  Since my hardware connect the first two channels to the "a" inputs and the last three inputs to the "b" channels the "b" channels cannot be read.  See the code HL_MonAdc1_Init below:   Is this limited by design or would it be better to set the correct ADC_CFG2_MUXSEL_MASK setting when the CreateSampleGroup method is called?  This would allow any combination of ADC inputs to be measured for single ended devices.

 

Thanks,

Kevin.

 

LDD_TDeviceData* HL_MonAdc1_Init(LDD_TUserData *UserDataPtr)

{

  /* Allocate LDD device structure */

  HL_MonAdc1_TDeviceDataPtr DeviceDataPrv;

 

 

  /* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */

  DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;

  DeviceDataPrv->UserData = UserDataPtr; /* Store the RTOS device structure */

  DeviceDataPrv->SampleCount = 0U;     /* Initializing SampleCount for right access of some methods to SC1n registers before first conversion is done */

  /* SIM_SCGC3: ADC1=1 */

  SIM_SCGC3 |= SIM_SCGC3_ADC1_MASK;

  /* PORTC_PCR10: ISF=0,MUX=0 */

  PORTC_PCR10 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));

  /* ADC1_CFG2: MUXSEL=1 */

  ADC1_CFG2 |= ADC_CFG2_MUXSEL_MASK;

  /* PORTC_PCR9: ISF=0,MUX=0 */

  PORTC_PCR9 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));

  /* ADC1_CFG2: MUXSEL=1 */

  ADC1_CFG2 |= ADC_CFG2_MUXSEL_MASK;

  /* PORTC_PCR8: ISF=0,MUX=0 */

  PORTC_PCR8 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));

  /* ADC1_CFG2: MUXSEL=1 */

  ADC1_CFG2 |= ADC_CFG2_MUXSEL_MASK;

  /* ADC1_CFG1: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,ADLPC=0,ADIV=3,ADLSMP=1,MODE=3,ADICLK=1 */

  ADC1_CFG1 = ADC_CFG1_ADIV(0x03) |

              ADC_CFG1_ADLSMP_MASK |

              ADC_CFG1_MODE(0x03) |

              ADC_CFG1_ADICLK(0x01);

  /* ADC1_CFG2: MUXSEL=0,ADACKEN=0,ADHSC=0,ADLSTS=0 */

  ADC1_CFG2 &= (uint32_t)~(uint32_t)(

                ADC_CFG2_MUXSEL_MASK |

                ADC_CFG2_ADACKEN_MASK |

                ADC_CFG2_ADHSC_MASK |

                ADC_CFG2_ADLSTS(0x03)

               );

  /* ADC1_SC2: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,ADACT=0,ADTRG=0,ACFE=0,ACFGT=0,ACREN=0,DMAEN=0,REFSEL=0 */

  ADC1_SC2 = ADC_SC2_REFSEL(0x00);

  /* ADC1_SC3: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CAL=0,CALF=1,??=0,??=0,ADCO=0,AVGE=1,AVGS=3 */

  ADC1_SC3 = (ADC_SC3_CALF_MASK | ADC_SC3_AVGE_MASK | ADC_SC3_AVGS(0x03));

  /* Registration of the device structure */

  PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_HL_MonAdc1_ID,DeviceDataPrv);

  return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the data data structure */

}

Outcomes