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DCU at 1024x768 and 32bpp (XGA resolution)

Question asked by Valter Minute on Apr 14, 2014
Latest reply on Apr 30, 2014 by Ioseph Martinez Pelayo

I’m working on the Vybrid display driver on Windows Embedded Compact and I have issues supporting the standard XGA resolution (that is reported as maximum resolution supported on the processor) at 32 bits per pixel.  We are using our custom modules and we developed the Windows CE BSP from scratch. We ported Linux BSP and currently run 3.2 kernel. On our 400MHz/500MHz platform the system works fine at 16BPP but increasing the bits per pixel leads to corrupted images with fifo overruns.  Using Linux on the 500MHz version image quality is better, but the on-screen image is still corrupted when the device is accessing USB, SD, flash memory etc. The reference manual report XGA as maximum resolution, but with no specs about the BPPs. On the other side the DCU chapter in the reference manual states that up to 4 layers can be used when the framebuffer is stored in DDR (we need to keep it in DDR because it’s too big for the internal RAM) and I'm currenty using just one layer.  I tried setting the DCU_MODE[DDR_MODE] bit or unsetting it but the behaviour is the same. It seems that DDR bus has enough bandwidth to support this resolution, but it seems also that the display internal pipeline is not able to collect data faster enough to deliver the expected output. For XGA mode the pixel clock is 65MHz. I use the PLL1PFD2 clock as source for DCU (452MHz) configuring it in CCM_CSCMR1. First divisor is 1, using 452MHz as frequency also for the DCU and second divisor is 7, leading to a 64MHz pixel clock, this respect the suggestion that DCU must run at at least 4x pixel clock. I enabled test mode for the DCU and I can see the color stripes, so I think that video output timings are ok. I have also no issue running the same resolution at 16bpp (same pixel clock, data also in DDR and same output parms), or driving the display at 32bpp at SVGA resolution (800x600 with 40MHz pixel clock, same memory layout for layer data).  That's why I suspect a memory bandwidth issue.  I'm checking the BSPs to understand why the issue is more noticeble on Windows CE than it is on Linux but still need to solve it on both operating systems. Is there a way to increase the bus bandwidth of the DCU controller to support high-resolutions at 32bpp?

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