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i.MX6 DQS gating delay

Question asked by Tom Saluzzo on Apr 11, 2014
Latest reply on Apr 30, 2014 by gusarambula

AN4467 page 21 states that The DQS gating includes a delay of up to 7.875 cycles. Delay value is combined from the DQS gating delay fields: (DG_DL_ABS_OFFSET/256 * cycle) + (DG_HC_DEL * half cycle).


When I review the register definition for Read DQS Gating Control Register 0 (MMDCx_MPDGCTRL0) it appears that I can only select a maximum of 7.0 cycles of delay.

DG_HC_DEL1 = 6.5 cycles [27:24]=1101. Note: The values 1110 and 1111 are reserved.

DG_DL_ABS_OFFSET1 = 0.5 cycle [22:16]=0x7F.


How I can set the register for > 7.0 cycles? Why are these upper two values reserved?


Does production silicon eliminate the limitation for MMDCx_MPDGCTRL0?

  • DG_HC_DEL1 = 1110 (7.0 cycles) and 1111 (7.5 cycles) are both reserved.