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i.MX6 ASRC clock divider calculations

Question asked by Awais Belal on Apr 11, 2014
Latest reply on Apr 16, 2014 by Wigros Sun


While looking at the i.MX6 manual (Rev. 1, 04/2013) at the start of page 655, the manual says "The clocks have the following restriction. If the prescaler is set to 1, the clock divider can only be set to 1 and the clock source must have a 50% duty cycle.". Now, if we look at the Freescale BSP the clock divider calculations for ASRC (get_clock_divider()) do not seem to take care of this fact and in case the prescaler is calculated as 0 the divider is set to 'ra - 1'. Is this a bug in the BSP or does the manual need updating? because I think they are contradicting. Kindly comment.