I'm running Mentor Graphics HyperLynx SI to simulate the DDR3 layout on the i.MX53 QSB design. I'm doing this so I can compare these results to our custom design's results. I looked in the IMX53AEC document to figure out the controller timings but I didn't have all of the data I needed for the HyperLynx tool. However, there was a DDR3 controller timing module already provided with the software (attached). Are the timing parameters set in this file for the 800MHz case correct? If not, could you provide me with the correct values or point me to a document where I could find (or calculate) them.
Original Attachment has been moved to: ddr3_ctl.v.zip