AnsweredAssumed Answered

The access method to PCIE_RC_BAR0 register.

Question asked by George Fukutomi on Apr 4, 2014
Latest reply on Apr 24, 2014 by George Fukutomi
Branched to a new discussion

Dear All,


We have planned the product which used i.MX6DL.

And, The product works PCIe on RTOS.


We are investigating how to use PCIe and are investigating the access method to PCI-Configuration space now.

In " i. MX 6Solo/6 DualLite Applications Processor Reference Manual, Rev.1, and 04/2013 ",

PCIE_RC_BAR0 register modification is described to be "Bits[3:0] are writable through the DBI."


Please tell me the PCIE_RC_BAR0 register modification method via DBI.

* I cannot find the materials about it.


Best Regards,